Tower and Jazz Announce Deep-Silicon-Via Technology
Tower Semiconductor Ltd. and its US subsidiary, Jazz Semiconductor, announced the availability of its proprietary Deep-Silicon-Via™ (DSV) technology available in its 0.18-micron SiGe BiCMOS (SBC18). The new offering provides a simpler, more innovative way to create a low-inductance ground required to reduce power consumption of power amplifiers (PA). Unlike older Through Wafer Vias used primarily with smaller wafer sizes in GaAs-based technology, the DSV is optimized for silicon 8-inch wafer manufacturing to significantly reduce the cost of the PA.
The DSV technology developed by Jazz utilizes existing equipment in its silicon CMOS wafer fabs and therefore can be scaled efficiently to high volumes without requiring complex thin wafer handling and processing. According to Strategy Analytics, power amplifiers in front-end modules of cell phones are expected to grow from 1.6 billion units in 2009 to 2.5 billion units in 2012. Today, Jazz is the leading supplier of silicon into the front-end modules of cell phones with market leading customers such as RFMD and Skyworks.
“We continue to invest in foundry technology for the front-end module by enabling silicon solutions of components that have traditionally been built in GaAs, helping customers reduce cost and increase integration levels. This new DSV technology is the latest offering in our Silicon Radio Platform that includes SiGe power amplifiers and SOI-based silicon switch technology,” said Marco Racanelli, Senior Vice President and General Manager, RF and High Performance Analog Business Group, Tower and Jazz Semiconductor.
A paper entitled “A Deep-Silicon-Via Ground for SiGe Power Amplifiers” will be presented by the company at the SiRF2010 conference in New Orleans, LA, on January 13, 2010. The paper will provide more details on the new technology including how it allows a more flexible layout than Through Wafer Via to result in smaller die size. DSV provides similar benefits to Through Wafer Via, yet it eliminates several thin wafer processing steps common with the older technology that can lower yields and increase cost. In addition to providing an ultra low parasitic inductance path to ground of approximately 2 pH which is 1 order of magnitude smaller than the Through Wafer Via inductance, it enables new creative ways for the designer in the PA design process. For example, new design features are using DSV to provide the function of the emitter ballast resistor; to improve linearity of gain and output power; to provide a short path to ground for shunt tuning elements; and using it for lateral shielding of circuit blocks.