A Broadband High Efficiency Class-J Power Amplifier for C-Band
A broadband power amplifier (PA) with a small chip size of 1.8 x 0.8 mm2 based on GaAs heterojunction bipolar transistor (HBT) technology is designed for C-Band. By setting the optimal load impedances in accordance with Class-J mode operation and incorporating a low Q output matching network, high efficiency is achieved. With a 5 V power supply and 2.9 V bias, a 3-stage PA demonstrates 30 ± 0.5 dB of small-signal gain and greater than 29.5 dBm of saturated output power with 36 percent power-added efficiency over its operating band from 5 to 7 GHz at room temperature.
One of the main challenges facing current satellite communication technology is power consumption, which impacts reliability and the efficient use of spectrum.1,2 Another major challenge is bandwidth. For a multi-band wireless communication system, wideband amplifier characteristics can enable more frequency bands with less hardware. In this context, broadband communication systems amplifiers came into being and have been widely applied in modern commercial systems.3-5
A single broadband high efficiency PA can provide savings in material costs, weight and power consumption. This is especially important for satellite communication at C-Band for operation during natural disasters, where C-Band frequencies provide more reliable connections.6,7 In addition, C-Band is useful for Wi-Fi devices and radar systems.
Linear, broadband and high efficiency power amplifiers are, therefore, key components of RF front-ends.8 For traditional wide bandwidth PAs, there is a tradeoff between efficiency and linearity. Generally, high efficiency is achieved by changing the static bias point to reduce the conduction angle and linearity is improved by suppressing higher harmonics.
To address this tradeoff, a second harmonic tuned high efficiency PA mode is employed.9-15 Recently, a newly developed Class-J mode of operation has demonstrated its potential for high efficiency and wide bandwidth applications while maintaining linearity.16-18 The new approach provides the same efficiency as conventional Class-AB PAs and addresses high second harmonic currents for improved linearity.
CLASS-J POWER AMPLIFIER AND MATCHING METHOD
In wireless communications, the traditional technique for achieving high efficiency power amplifiers is to operate in deep Class-AB mode.19-21 Fourier series analysis of the Class-AB power amplifier waveform shows that it has a high second harmonic current level.22
To obtain a sinusoidal collector voltage waveform at the fundamental frequency of an HBT, deep Class-AB operation requires a resistive load at the fundamental frequency and a short-circuit termination for all harmonics, which also affects the output power and reduces efficiency. In a practical design, the second harmonic shorting terminal is accomplished by using a trap at the collector of the output transistor operating at the second harmonic frequency.23-26
The wave trap is a parallel branch composed of a capacitor and an inductor in series to achieve resonance at the second harmonic. Due to the influence of operating frequency and circuit parasitic parameters, the second harmonic termination tends to become capacitive. Therefore, the main factor affecting efficiency is the deviation of the harmonic termination. In addition, shorting the second harmonic requires a high Q trap, which is contradictory for wide bandwidth.
Thus, to achieve a wide bandwidth with maximum efficiency, the PA design must leverage the second harmonic, while avoiding direct use of a second harmonic resonant circuit. The method used in such a design is the Class-J mode PA.
Class-J PA Design
A simplified schematic of the three-stage PA is shown in Figure 1. The transistor sizes of the first, second and third stages are 200 µm2, 420 µm2 and 2,600 µm2, respectively. The passive components have the following values: C1 = 3 pF, R1 = 400 Ω C2 = 2 pF, C3 = 3 pF, L1 = 0.5 nH, C4 = 1.6 pF, R2 = 2000 Ω C5= 1pF, C6 = 2 pF, L2 = 0.05 nH, C7 = 8 pF, C2f0 = 3.2 pF, Ctrap = 0.34 pf, Ltrap = 0.23 nH, L4 = 0.15 nH, C8 = 0.6 pF, L5 = 0.18 nH and C9 = 0.63 pF.
The first stage is biased in Class A mode for the highest linearity. The second stage operates in shallow Class-AB mode for higher linearity and better efficiency. The third (output) stage operates in Class-J mode for bandwidth extension and linearity enhancement.
To realize better flat gain and linearity, AM-to-AM and AM-to-PM flatness characteristics are important. The output stage operating with low quiescent current bias and Class-J output matching exhibits gain expansion and lagging phase shift characteristics. To compensate for these nonlinearities, the second stage is designed to have gain compression and leading phase shift characteristics, and the first stage is optimized to deliver flat gain and phase shift. Hence, the PA achieves flat AM-to-AM and AM-to-PM performance over a wide range of output powers (see Figure 2).
Class-J Mode of Operation
Proper output matching network (OMN) design is essential for optimum PA performance. The Class-J load for the maximum fundamental voltage component is determined from the optimal Class-B fundamental load.27 Figure 3 shows the OMN circuit and its characteristic, where a parallel capacitor is added at the collector of the output transistor so that the output voltage waveform is 45 degrees different from the original voltage waveform.
The expressions for the current and voltage waveforms are:
Where θ is the conduction angle.
Equations (3) and (4) represent the fundamental impedance ZL1 and the second harmonic impedance ZL2, respectively.
Where Ropt is the optimal load impedance with a small fundamental wave at the maximum current.
Equation (5) describes the capacitance value C2f0 of the output terminal at the second harmonic. Note that the fundamental and second harmonic impedance traces should have opposite directions.28
To determine the optimum load impedance at high power, the loads are modified through large-signal harmonic balance simulations for the third stage transistor nonlinear output capacitance, which affects the capacitance value C2f0.
Output matching is a two-stage L-type low-pass network to expand the bandwidth, shown within the blue dotted line in Figure 3a. The minimum Q of the OMN is expressed in Equation (6), where Rload is 50 Ω.
It can be seen in Equation (7) that the series LC tank, (Ctrap and Ltrap) for the third harmonic (3f0) trap creates a short-circuit load at 3f0.
Figure 3b shows the load impedance trajectories. The fundamental theoretical impedance (Ropt) of the OMN is shown in red. The second harmonic impedances from 10 to 14 GHz are nearly 1.178 x Ropt. The third and higher-order harmonic impedances at the load plane are also terminated to short circuits. The optimum fundamental and second harmonic impedance design approach controls the bandwidth with a low Q OMN and by determining the impedance transformation, independently.
PA FABRICATION AND PERFORMANCE
Figure 4 is a microphotograph of the PA with a chip size of 1.8 × 0.8 mm. The total quiescent current is approximately 132 mA with a supply voltage of 5 V and a bias voltage of 2.9 V. RF input and output pads are bonded using 25 µm diameter gold bond wires to 50 Ω microstrip. Power supply pads are wire-bonded to the printed circuit board traces.
With a continuous wave input signal, the experimental results are shown in Figures 5 through 9. Simulated and measured scattering parameters of the PA are shown in Figure 5. It achieves a small-signal gain of 30 and 31.5 dB, input return loss of 15 and 35 dB and an output return loss of 5 and 18.5 dB at 5 and 7 GHz, respectively. Measured S-parameters agree well with the simulation. Differences are attributed to inaccurate bond wire modeling, board parasitics and crosstalk due to the board layout.
Maximum output power over the band is between 29.5 and 30 dBm, while power-added efficiency (PAE) is between 36 and 42.7 percent (see Figure 6)
Simulated and measured AM-to-AM and AM-to-PM conversion at 6 GHz are plotted in Figure 7a. The PA exhibits a measured AM-to-AM conversion of 29.5 dB on average with 0.5 dB variation from 0 to 30 dBm input power. The variation of AM-to-PM in the fabricated PA is 1 to 5 degrees. For a 1024 QAM modulation signal, Pout meeting an error vector magnitude (EVM) of –40 dB is 16.7, 18.2, 20.6, 19.5 and 17.8 dBm at 5.0, 5.5, 6.0, 6.5 and 7.0 GHz (see Figure 7b).
Figure 8 shows the measured saturated output power (Psat) and output 1 dB compression point (OP1dB) from 4.4 to 7.6 GHz, while Figure 9 shows the measured second and higher-order harmonic suppression with an output power of 27 dBm at 6 GHz.
Compared with other reported results, this design generally exhibits a wider bandwidth corresponding with high output power (see Table I). The topology of a Class-J PA is simpler than that of Class-F or Class-AB. The Class-J PA designed here is less affected by losses in integration.
TABLE I COMPARISON WITH OTHER STATE-OF-THE-ART PAs
A wideband 5 to 7 GHz Class-J GaAs HBT PA is designed for high efficiency. To obtain wide bandwidth, the OMN is based on a low Q impedance transformation. The PA with a 1.44 mm2 chip area exhibits a measured small-signal gain of 30 dB average with 0.5 dB variation from 5 to 7 GHz. In addition, the design techniques deliver more than 29.5 dBm Psat associated with 36 percent of PAE. These results demonstrate that the Class-J mode PA achieves high efficiency over a wide bandwidth with excellent linearity.
This work was funded in part by the Key-Area Research and Development Program of Guangdong Province (Grant No. 2018B010115001), in part by the National Natural Science Foundation of China under Grant 61974035 and in part by the Guangdong Local Innovative Research Team of the Pearl River Talent Program under Grant 2017BT01X168.
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