Microwave Journal
www.microwavejournal.com/articles/39177-inp-cmos-heterogeneous-integration-for-the-next-generation-of-wireless

InP + CMOS Heterogeneous Integration for The Next Generation of Wireless

November 14, 2022

Early discussions of the capabilities that will enable 6G envision materials and devices operating above 100 GHz. Indium phosphide (InP) is one semiconductor technology with the characteristics to achieve the required speed, efficiency and output power for sub-THz frequencies. To serve global wireless markets, InP process technology must be commercialized to maintain the performance advantages while able to be mass produced at the requisite prices to meet market needs. To develop InP into a mature technology, imec is researching nano-ridge engineering to grow InP on Si. Then, to integrate all the semiconductor components into a multi-function communications circuit, imec is exploring printed circuit board (PCB), 2.5D and 3D packaging technologies.

Every 10 years heralds a new generation of mobile communications. Over the generations, the number of subscribers has grown tremendously, each subscriber consuming an ever-increasing amount of wireless data. In the beginning, we were happy to send a text message. Today, 5G has achieved more than 1 billion human-to-machine and machine-to-machine connections with peak data rates of 10 Gbps. 5G is also an inflection point: in addition to needing more connections with data rates at ever higher speeds, the technology has the potential to enable new applications such as autonomous driving and holographic presence. These demands on the radio technology will drive 6G, envisioned for launch in 2030. By then, we will expect peak data rates greater than 100 Gbps with extreme coverage, pervasive connectivity and capabilities undefined today.

GENERATING EFFICIENT POWER ABOVE 100 GHz

To enable these very high data rates, the telecom industry has been increasing channel bandwidth, which pushes operating frequencies higher. The vision for 6G is that the frequencies above 100 GHz will be tapped, starting with D-Band around 140 GHz. The biggest semiconductor challenge for circuits above 100 GHz is achieving sufficient gain, output power and efficiency. For both CMOS and SiGe amplifiers, the saturated output power at D-Band does not exceed 15 dBm, with efficiency typically below 10 percent. This is very low for communications systems using popular modulation schemes like 64-QAM. To achieve the required linearity, the power amplifier (PA) is backed off more than 6 dB below its saturated output capability. As the output power is reduced, efficiency drops more than linearly.

InP offers much better performance at these frequencies: output power greater than 20 dBm with efficiencies above 20 percent—even to 30 percent. For arrays where the transceiver footprint is restricted to a half-wavelength or the number of antenna elements is limited, InP enables 2× lower power consumption and 2× smaller footprint (see Figure 1).1

Figure 1

Figure 1 PA Tx power vs. number of antenna elements for a constant array EIRP, comparing InP, SiGe and CMOS PAs.

BRINGING InP TO MATURITY

Creating InP heterojunction bipolar transistors (HBTs) for 100 GHz and higher frequency systems requires, first, a mature and cost-efficient InP technology and, second, an approach to integrate InP and Si components into a complete system. To meet both challenges, heterogeneous integration of a III-V material such as InP with CMOS is key. CMOS will be the predominant technology used for calibration, control, beamforming and data conversion.

To meet the speed, efficiency and output power needed for these wireless systems, imec envisions InP HBTs fabricated on a 300 mm (12 in.) Si wafer platform. Today, compared to Si, InP wafers are small—under 6 in.—and devices are fabricated using serial processes such as e-beam for gate lithography, and the contact metallization is gold-based. InP is brittle, one of the most prominent challenges. None of these are compatible with CMOS fabrication.

Figure 2

Figure 2 Nano-ridges fabricated with InGaAs.

To use InP with Si, imec is researching ways to transfer III-V materials onto Si. Due to the large lattice mismatch between both materials, growing InP on Si usually introduces defects, mainly threading dislocations and planar. These induce leakage currents that can dramatically deteriorate device performance or impair reliability because the defects capture and release carriers at RF frequencies. To address the defects generated when directly growing InP on Si, imec is developing a fabrication process called nano-ridge engineering, which selectively grows the III-V material in pre-patterned structures or trenches in the Si (see Figure 2). These high aspect-ratio trenches are very effective, trapping the defects in the narrow bottom part and growing high-quality, low defect material out of the trench. At the same time, overgrowing the nano-ridge widens it near the top, forming a solid base for a device stack. Reducing the pitch between nano-ridges enables them to merge to create a local plate of III-V material.



Recently, imec demonstrated box-shaped nano-ridges fabricated with 53 percent InGaAs, which efficiently trapped the threading dislocations in the trench. The nano-ridges were successfully grown both standalone and in a guided template. imec is using the same approach—combining InGaAs nano-ridge engineering with insights from earlier demonstrations of InGaP/GaAs nano-ridge HBTs—to develop a heterostructure stack for 140 GHz applications.

Other than direct growth such as nano-ridge engineering, InP can also be placed on Si using small InP substrates as the starting material. Called wafer reconstitution, high-quality InP substrates would be diced and sorted into non-patterned tiles during wafer fabrication, with the tiles subsequently attached to a Si wafer, planarized and processed in the fab. Table 1 assesses the performance, cost and heterogeneous integration potential of the direct growth and wafer reconstitution options compared to native InP substrates.

Table 1

SYSTEM LEVEL CO-INTEGRATION

Obtaining a mature and cost-efficient InP technology through direct growth or wafer reconstitution is only part of the challenge, however. The resulting components need to be integrated into a complete system comprised of various building blocks in III-V and CMOS technologies, such as InP HBTs for PAs or CMOS for the beamforming transceiver. This poses a set of integration challenges. imec is looking into monolithic (2D) integration of III-V and Si devices in the same plane and 2.5D and 3D integration approaches for heterogeneous integration.

State-of-the-art PCB technology is continually being optimized to support higher frequencies, including reducing the pitch and optimizing materials and layout. 2.5D integration uses Si interposers—a chip or layer with lithography-defined connections and possibly through Si vias—to connect III-V and Si die. While this technology has been optimized for high speed digital applications (see Figure 3), it requires development to optimize it for RF. imec is evaluating dielectrics and various thicknesses of the metal layers to achieve low loss, high frequency interconnects. Options include high resistivity Si substrates or thick dielectric layers to distance the metal layers from the lossy substrate; also, a very thick redistribution layer, an extra metal layer to reduce metal loss. imec is also developing the capability to integrate high-quality passives for certain circuit applications.

Figure 3

Figure 3 Top view of an RF interposer with a Si stacked top die.2

2.5D AND 3D: KEY FOR HETEROGENEOUS INTEGRATION

Why 3D integration? As frequency increases, wavelength decreases and the area of an antenna array shrinks accordingly. Above 100 GHz, the antenna pitch gets smaller than the front-end circuit pitch, as the area of mmWave RFICs hardly shrinks. So the footprint of the antenna array sets the size constraints; to fit everything underneath the antenna, heterogeneous integration using the third dimension becomes necessary.

Over the last decade, tremendous progress has been made with 3D interconnects, particularly reducing the interconnect pitch for wafer-level applications—i.e., wafer-to-wafer, die-to-wafer (see Figure 4).3 For wafer-to-wafer or hybrid bonding, imec has achieved pitches below 1 μm and can push this down to below 500 nm. The same trend to reduce the pitch holds for die-to-wafer bonding and die stacking using micro-bumps.

Figure 4

Figure 4 3D interconnect technology roadmap. Includes data from H.-S. Philip Wong, et al.4 and Techinsights.

Several challenges are shared between the two integration schemes for >100 GHz cases. First, they both rely on having a fine via or micro-bump pitch below 100 μm. Second, they must accommodate large numbers of connections for routing the RF, DC, IF and digital signals. Finally, both the trace and space dimensions need to be much smaller than 50 μm, preferably between 5 and 10 μm.

There are also differences between the two schemes (see Figure 5). In the case of 2D or 2.5D integration, the III-V device sits next to the CMOS IC, enabling better thermal management because both die can be in direct contact with a heat sink. The disadvantage is that the footprint may need to be extended in one dimension for some applications, meaning this architecture only enables 1D beam steering. In comparison, 3D integration enables all the die and circuits to fit under the antenna and enables 2D beam steering across a hemisphere. 2D beam steering is necessary for 5G and similar applications to minimize penetration losses and increase reach. With 3D, thermal management is more challenging and, of course, 3D integration is more complex, having unique processing challenges.

Figure 5

Figure 5 2/2.5D integration using a Si interposer to connect the III-V and Si die (a). 3D integration where the III-V die are stacked on the Si (b).

SYSTEM TECHNOLOGY CO-OPTIMIZATION

The choice of integration and packaging solutions ultimately depends on the application. Because so many options are available, imec has launched a system technology co-optimization (STCO) program to guide the technology choices at the system level. The STCO methodology uses architecture and application constraints, assessing signal loss, bandwidth, heat dissipation, mechanical stability and cost. Considering these parameters together enables trade studies to determine the appropriate technology and device designs for 6G.

References

  1. C. Desset et al., “InP/CMOS Co-integration for Energy Efficient sub-THz Communication Systems,” IEEE Global Communications Conference, December 2021.
  2. X. Sun et al., “Cost-Effective RF Interposer Platform on Low-Resistivity Si Enabling Heterogeneous Integration Opportunities for Beyond 5G,” IEEE 73rd Electronic Components and Technology Conference, June 2022.
  3. E. Beyne, “3D System Integration: Technology Landscape and Long-Term Roadmap,” Roadmap on 3D Interconnect Density Forum, International Solid-State Circuits Conference, February 2021.
  4. H.-S.P. Wong et al., “A Density Metric for Semiconductor Technology,” Proceedings of the IEEE, Vol. 108, No. 4.