Microwave Journal

EdgeCortix/Renesas Collaboration to Deliver Enhanced Compiler for the Renesas DRP-AI AI-Accelerator

July 12, 2022

EdgeCortix® Inc., an innovative fabless semiconductor design company with a software first approach, focused on delivering class-leading compute efficiency and latency for edge artificial intelligence (AI) inference, announced a collaboration with Renesas Electronics Corporation.

Through this collaboration, EdgeCortix has taken its industry leading heterogeneous platform-based compiler framework MERA and developed a new compiler, dynamically reconfigurable processor for AI (DRP-AI) TVM for Renesas' DRP-AI1 accelerator. The new compiler is available with associated software and tools and works in combination with Renesas' DRP-AI tools.

"We are eager to apply the power of our MERA compiler across many heterogeneous environments, including leading FPGA boards, EdgeCortix's own custom AI-Inference ASIC and today, integration with Renesas' DRP-AI," said Sakyasingha Dasgupta, founder and CEO of EdgeCortix. "We are very pleased that Renesas has realized the value, utility and performance that our MERA solution offers in developing the compiler for DRP-AI. By applying EdgeCortix's MERA compiler technology to DRP-AI TVM, this combination will create significant business opportunities and value for both Renesas and their end customers in four key functional areas. Namely, Expanded Model Support, ML Framework Expansion, Support for Floating-point 16 and overall Performance Enhancements."

EdgeCortix Delivered Key Business Outcomes via MERA collaboration with Renesas DRP-AI Tool:

  • Expanded Model Support: More robust AI model support (20+ models explored) with significantly enhanced flexibility and end-user ease-of-use enhancement
  • ML Framework expansion: Future proofing the DRP-AI product utility, by adding PyTorch support and making the ONNX support more robust. TensorFlow support to be added in ongoing future work
  • Support for Floating-point 16 bit to MERA and extended OSS tool Apache TVM. Lower-precision support being added in ongoing future work
  • Performance Enhancements: Improved performance especially for models with operators shared between host CPU and DRP-AI (a new feature added with this integration work).

"We recognized immediately the value of adding the MERA compiler and associated tool set to the RZ/V MPU series, as we expect many of our customers to implement application software including AI technology," said Shigeki Kato, vice president, Enterprise Infrastructure Business Division at Renesas. "As we drive innovation to meet our customer's needs, we are collaborating with EdgeCortix to rapidly provide our customers with robust, high performance and flexible AI-inference solutions. The EdgeCortix team has been terrific, and we are excited by the future opportunities and possibilities for this ongoing relationship."