Microwave Journal
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5G Power Amplifier Design and Modeling for mmWave GaN Devices

July 12, 2019

Advanced semiconductor technology plays an important role in evolving RF and microwave applications for 5G and SATCOM where the next generation of systems is moving towards mmWave frequencies. Support of design flows and model availability for these semiconductor technologies is critical to designers for successful product development. In response, EDA software vendors offering MMIC and RFIC design solutions must work closely with leading foundries to ensure their products provide increased integration and higher performance while lowering cost and size requirements.

This article highlights techniques supporting device modeling of III-V wide bandgap semiconductor technology, specifically the United Monolithic Semiconductors (UMS) GH25 (0.25 µm gate length), GaN on SiC process for mmWave power amplifiers (PA) targeting new communication and defense systems. Model accuracy is validated through simulation and measurements of multiple designs that were developed using the GH25 process design kit (PDK), serving as a development framework that will guide future work in support of evolving process node technologies like the GH15, 0.15 µm GaN on SiC process currently in the qualification phase. Processes such as this are well suited for 5G applications as demonstrated by a 10 W Ka-Band (29.5 to 36 GHz) PA and a 2 W front-end module (24 to 30 GHz) that integrate the GaN on SiC PA with other RF functions implemented with a GaAs process.

GaN Technology and Modeling Challenges

Short gate-length GaN devices have demonstrated excellent performance for mmWave PAs. Offering higher operating voltages and reduced device parasitics, these GaN transistors provide higher output power densities, wider bandwidths and improved DC-to-RF efficiencies than their GaAs counterparts. In order to take advantage of this enhanced performance, designers need a scalable model that accurately captures the complex behaviors of the device during circuit simulation. The behavior of the trapping and thermal phenomena in GaN devices represents a real challenge for transistor modeling.

Devices can be represented in simulation by various methods, including compact, physics-based or behavioral models. Physics-based models incorporate physical aspects of the device to predict performance but are too complex for circuit simulation. Behavioral models are generally used in system simulations to represent an entire radio block but do not provide the necessary detail to support the actual amplifier design effort.

Compact models, based upon curve fitting, use functions and parameter values that produce the best fit to measured data, such as pulsed I/V and S-parameters. It is critical for the model to accurately replicate the transistor response over its entire range of operation in order to produce reliable circuit simulations. Parameters in these empirical models have no fundamental basis, but the physical consistency of the model equations is necessary to guarantee a good model extrapolation for designs lying outside the model characterization range.

There has to be a strong connection between technology/device development and the device modeling effort. The characterization and modeling methods implemented need to be validated through a well-established process/model qualification procedure that has been proven to yield reliable device models for the foundry’s family of semiconductor processes (see Figure 1). For GaN devices, the know-how and background from developing GaAs technologies have guided the current model development efforts in many cases. Established lower frequency GaN processes have also helped advance the state of device modeling for the latest short-gate devices. Nonlinear models are extracted taking into account traps phenomena1 and transistor self-heating. In addition to electrical characterization, the UMS modeling team performs a comprehensive study of the thermal device behavior and other non-stationary effects to improve the quality of their nonlinear device modeling.

Figure 1

Figure 1 Main steps to active device modeling incorporating measurements, model extraction and validation.

This fitting process and characterization data supports the development of transistor models used by software design tools, such as the NI AWR Design Environment platform, to predict the overall MMIC behavior when these devices are embedded in a matching/biasing network and excited by RF signals. Models are organized into PDKs supported in Microwave Office circuit design software with electrical and physical layout information to enable the design of MMICs using the GaN or GaAs process.

Model/PDK Development

Characterizing the active device to develop a scalable transistor model is the most important step in developing a process design kit. A scalable model allows the designer to vary the device periphery (gate width and number of gate fingers) for desired performance. One challenge is developing models accurately over the desired range of gate peripheries and operating conditions.

A device modeling procedure based on device characterization through measurement, model extraction via empirical fitting, and validation through device- and circuit-level simulation as illustrated in Figure 1 has been implemented here. The foundry also provides a family of models dedicated to multiple uses. For example, considering quarter micron technology, scalable linear models supporting low-noise amplifier (LNA) designs include noise characterization over a 10 to 20 V drain bias. A hot, nonlinear model for high power applications is scalable with medium to large gate peripheries, offering electrothermal model accuracy over a 10 to 30 V drain bias. A cold nonlinear model dedicated to switch applications is available for 2 topologies (serial and parallel) with model accuracy for various gate voltages.

Model Extraction

The typical equivalent circuit of a compact transistor model is shown in Figure 2. This model includes extrinsic linear elements and intrinsic nonlinear elements. Firstly, the transistor’s extrinsic parasitic elements (R, L and C) are extracted in order to de-embed the S-parameter data to the intrinsic reference plane and to extract the intrinsic parameters (Cgs, Cgd, Gm, Gd, Cds, Ri, Tau, Rgd) using explicit equations. The accurate extraction of the parasitic elements is based on both cold field-effect transistor (FET) S-parameter measurements (Vds = 0) and electromagnetic (EM) simulations of the device feed manifold.

Figure 2

Figure 2 Nonlinear sources in equivalent circuit model with extrinsic parasitics.

The next step is to determine the value of the intrinsic elements. For GaN devices, the main nonlinearities are the drain-to-source current and the gate-to-source and gate-to-drain capacitor, as well as the input Schottky diode behavior.

The high-electron mobility-transistor (HEMT) is affected by trapping phenomena. Traps are locations within a semiconductor that limit the movement of holes, mostly due to crystalline imperfections in the GaN material like impurities in the crystal lattice and dangling bonds on the surface or at interfaces, as shown in Figure 3. These imperfections generate trap centers within the bandgap of a semiconductor.2 The parasitic charge of the traps affects the density of the two-dimensional electron gas channel3 in GaN-based transistors.

Figure 3

Figure 3 Locations of trapping centers in wide bandgap semiconductors.

A variety of trapping effects in aluminum GaN (AlGaN)/GaN HEMTs have been observed, including transconductance frequency dispersion, current collapse, gate- and drain-lag transients and restricted microwave power output. The dominant drain lag effect depends on both the voltage bias and the channel temperature, and it is traditionally taken into account by using quasi-isothermal pulsed I/V and pulsed S-parameter data instead of continuous wave (CW) measurements. The pulsed I/V S-parameters technique measures the S-parameters during the on-cycle of a fast pulse with a low-duty cycle. Instantaneous gate and drain biases are moved from a chosen steady quiescent bias to another point on the I/V plane to better replicate operational behavior where the thermal and trap conditions are set by the quiescent bias conditions (see Figure 4). Pulse widths are kept short enough to avoid a strong temperature variation during the pulse duration, so that the transistor’s pulsed I/V measurements are obtained under quasi-isothermal conditions.

Figure 4

Figure 4 Pulsed technique for device characterization.

The data obtained with this measurement protocol is then used to fit the parameters of in-house equations, developed for improved accuracy of the source current derivatives (Gm/Gd) over large values of Vgs and Vds. Similarly, UMS gate charge equations improve the description of the capacitors variation over the gate and drain voltages.

Nevertheless, the pulsed I/V and S-parameter characterization are not sufficient for describing the drain lag in GaN transistors. Indeed, the trapping phenomena in GaN HEMTs present several time constants, some of them shorter than the shortest pulse duration available for test. The charge of these traps directly depends on the voltage pick across the device under RF dynamic operations, this is taken into account in the model by a dedicated module based on envelope detection.4

Thermal Modeling

The thermal behavior of high-power GaN devices must be taken into account. The thermal impedance is determined with the use of 3D finite-element method (FEM) simulation and introduced into the model using an electrical description in order to automatically calculate the junction temperature during the electrical simulation, as described in reference 4 (see Figure 5). The model is valid over a backside temperature from −40°C to 120°C. This electro-thermal model enables design at different temperatures and simulation of the junction temperature in both CW and pulsed operations.

Figure 5

Figure 5 Electrical description of the thermal behavior of the device contained in the model.

Model Validation

The resulting model is validated by comparing simulation results for a range of operating conditions and gate peripheries (from 2 x 30 µm to 10 x 300 µm for this quarter micron process). Load-pull measurements are used to validate the model’s ability to predict device performance for different load impedances. For validation, the model is used for a fixed device periphery at various bias conditions, input power levels and excitation frequencies. Load-pull simulations in Microwave Office software can be readily compared to measured results obtained in the test lab. Measured figures of merit, such as gain, output power, power-added efficiency (PAE) and drain current, are captured in Figure 6 for a 1 mm device operating at 10 GHz, and show excellent agreement with the simulation results at several backside temperatures sweeping from −40°C to 125°C. The load positions for optimum power, PAE or linearity are also well-simulated as demonstrated in Figure 6 by the output power contour load pull.



7m27f6.jpg

Figure 6 GH25-10 heterostructure FET (HFET) model validation at 10 GHz on 8 x 125 µm transistor: line = model, circles = measurements.

PDKs for Circuit Simulation

Active device models and passive on-chip components, along with their parametric layout cells (PCells) are organized into PDKs to support MMIC development using these technologies. These PDKs provide simulation-ready device models to design ICs and generate layout masks for fabrication. The PDKs for Microwave Office software are available directly from UMS and include a layout process file (LPF), which defines the material stackup and metallization layers for EM simulation. Designers can adjust the parameters of the active and passive device models, such as gate width/number of fingers or capacitor/inductor values. In addition to a parameterized PCell, models come with a symbol representation for schematic editing. Figure 7 shows components from the GH25 PDK placed in a Microwave Office schematic. A similar PDK will be developed for the GH15 and GH10 process nodes as the finalized models are qualified at UMS.

Figure 7

Figure 7 Various components from UMS GH25 PDK in NI AWR Design Environment software.

Microwave Office software offers a pre-configured example project for FET characterization that designers can use to investigate basic functioning of the transistor model before beginning their design. The default device can be replaced with a nonlinear hot FET model and simulations to observe the device DC and RF performance can immediately be performed. After adding the UMS PDK to the process library, the project layout browser will be populated with the UMS LPF file. The PDK models will appear in the elements browser for user placement in the schematic design window. The FET characterization project is configured to simulate standard device measurements, including DC I/V curves, S-parameters, single- and two-tone swept power such as gain, output power and PAE and power-dependent output load-pull contours (see Figure 8).

Figure 8

Figure 8 Simulation results for a single (8 x 75 µm) 0.25 µm GaN HEMT device, characterized for DC, small- and large-signal RF performance.

With the 0.25 µm PDK installed, the designer is able to apply a combination of linear/nonlinear and load-pull analyses. The recently introduced network synthesis feature in Microwave Office software supports the development of the bias and matching networks from frequency response (S-parameters) or load-pull analysis to achieve optimum power, linearity and/or efficiency performance. This capability was used to determine the appropriate source/load impedance for an 8 x 75 µm (0.25 µm) GaN device operating at 18 GHz, shown in Figure 9. An approximate short circuit was presented to the output of the device at the second harmonic (36 GHz) via a shunt capacitor to improve the peak PAE (~36 percent).

Figure 9

Figure 9 Simulation results for an 18 GHz PA based on a single (8 x 75 µm) 0.25 µm GaN HEMT device.

GaN Technology for 5G Applications

Figure 10

Figure 10 Typical performance of an 8 x 75 µm 0.15 µm transistor at 18 GHz with the output impedance set for optimum Pout and PAE using load-pull measurements.

Figure 11

Figure 11 AM/AM and AM/PM performance of a 8 x 50 µm 0.15 µm transistor at 30 GHz exhibits low phase deviation indicating good linearity.

Figure 12

Figure 12 Example of a 5G 2 W high-power front-end operating from 24 to 31 GHz.

The GH15 technology5 is fabricated on a 4 in. AlGaN/GaN on 70 µm thick SiC substrate wafer. The source-terminated field-plate transistors offer more than 3 W per mm power density at 30 GHz for high-PA (HPA) designs. The process also supports dedicated transistor topologies for cold FET applications such as the switches needed in a front-end module. The typical performance for an 8 x 75 µm GH15 device at 18 GHz is shown in Figure 10. Using load pull to provide the optimum impedance termination for output power and PAE, the transistor exhibits 4 W/mm output power, 13 dB associated power gain (with the Zsource = 50 Ω) and a maximum PAE of nearly 60 percent.

Good transistor linearity is important, especially for telecom applications. A measure of the device’s potential linearity can be obtained through the CW measurements of the transistor’s AM/AM and AM/PM performance as a function of output power. Sweeping the input power driving a 0.15 micron transistor at 30 GHz, which is terminated with a load for maximum power, the device demonstrates low-phase deviation indicating good linearity (see Figure 11).

A 2 W front-end module operating at 24 to 31 GHz covering the 28 GHz 5G band was developed to demonstrate the performance capabilities of the 0.15 micron AlGaN/GaN on SiC technology for mmWave frequencies.6 Two technologies were combined into a plastic package. The module shown in Figure 12 includes the PA and switch realized with 0.15 micron GaN technology and the 0.15 micron GaAs receiver. This device is for telecommunications applications such as high-throughput fixed-access wireless, time-division duplex (TDD) and phased-array antennas.

CW measured power results of the transmit path demonstrate a maximum output power higher than 2 W (33.5 dBm) with 24 percent PAE and 36 dB of insertion gain in the transmit path over the 24 to 31 GHz spectrum. The receiver path provides a noise figure (NF) of 3.6 dB with an associated gain of 20 dB with maximum output power of 30 mW (15.5 dBm). The high-power front-end (HPFE)/Tx linearity has been investigated with several M-quadrature amplitude modulation (M-QAM) signals with 25/50 and 100 MHz channel spacing and using digital predistortion (DPD) leading to 48 dBc adjacent-channel leakage-ratio (ACLR) and 40 dB mean-squared error (MSE) for average output powers ranging from 17 dBm to 25 dBm. The linearity performances have been compared to the ones obtained with two other linear GaAs amplifiers dedicated to point-to-point telecommunications applications: the HPFE presents similar linearity performances associated with a higher efficiency.

An optimized tradeoff in terms of integration, electrical performance and cost was achieved using the mixed-technologies approach, shown in Figure 13. The frequency response of the transmit path shows a gain between 34 to 36 dB over the band, with an output power close to 32 dBm (at 5 dB compression). The PAE varies in the band between 22 to 24 percent (at 5 dB compression). The receive path shows 20 dB gain with a typical NF from 3 to a maximum of 4 dB.

Figure 14 is the large-signal modulated results including ACLR for the transmitter with and without the polynomial DPD. The 256-QAM modulated signal specifications are shown in the lower bottom table, with channel spacing of 56 MHz, RF frequency of 28 GHz, average output power of 23 dBm and peak-to-average power ratio (PAPR) of 9 dB. The top constellation diagram of the Tx output with DPD shows the relevance of a full characterization.

Another example of a GaN Ka-band PA also demonstrates the performance of this process at 29.5 to 36 GHz, in the vicinity of the 5G upper mmWave spectrum (37 to 43.5 GHz) (see Figure 15). The measured performance (CW and 25°C) shows a peak output power greater than 10 W, PAE greater than 25 percent and power gain at Psat greater than 21 dB. The next step at the product level will be to extend the frequency band of this amplifier family to cover the 37 to 40 GHz band for 5G.

7m27f13.jpg

Figure 13 Simulation results for the 5G 2 W HPFE.

Conclusion

Figure 14

Figure 14 Large-signal modulated Tx results showing adjacent channel regrowth with and without DPD.

This article has described emerging GaN on SiC semiconductor technology targeting mmWave frequencies for applications such as 5G. The performance of MMICs designed with this GaN process was demonstrated with two examples: a 10 W Ka-Band (29.5 to 36 GHz) PA and a 2 W integrated front end for 24 to 30 GHz combining a GaN PA with other GaAs functions in a plastic package for 5G applications.

The success of the circuit design was guaranteed by the use of accurate, nonlinear FET models, inclusive of trapping and thermal effects and based on measurements. Load-pull measurements were compared with simulated results to validate model accuracy. The resulting models were organized into a PDK, along with the corresponding layout PCells for use in designing MMICs in a simulator such as Microwave Office software. Along with the UMS PDKs currently available for Microwave Office software, the foundry will fully release the 0.15 micron process in 2019 and is also developing a 0.1 micron GaN process.

References

  1. O. Jardel, F. De Groote, C. Charbonniaud et al., “A Drain-Lag Model for AlGaN/GaN Power HEMTs,” Proceedings of the International Microwave Symposium, Honolulu, Hawaii, 2007, p. 601.
  2. A. Benvegnù, “Trapping and Reliability Investigations in GaN-based HEMTs Electronics,” Université de Limoges, 2016.
  3. S. D. Nsele, L. Escotte, J. G. Tartarin, S. Piotrowicz and S. L. Delage, “Broadband Frequency Dispersion Small-Signal Modeling of the Output Conductance and Transconductance in AlInN/GaN HEMTs,” IEEE Trans. Electron Devices, Vol. 60, No. 4, April 2013, pp. 1372–1378.
  4. C. Chang et al., “Nonlinear Transistor Modeling for Industrial 0.25 μm AlGaN-GaN HEMTs,” 8th European Microwave Integrated Circuits Conference, October 2013.
  5. V. Di Giacomo-Brunel et al., “Industrial 0.15 μm AlGaN/GaN on SiC Technology for Applications Up to Ka-Band,“ 13th European Microwave Integrated Circuits Conference, September 2018.
  6. M. Ayad et al., “Mixed Technologies Packaged High Power Front-End for Broadband 28 GHz 5G Solutions,” 13th European Microwave Integrated Circuits Conference, September 2018.
Figure 15

Figure 15 Output power and PAE over temperature from 25°C to 120°C.