Clocking the RF ADC with Phase Noise Instead of Jitter
When designing an RF sampling receiver, system designers can use frequency domain analysis to better specify the phase noise requirements of the external sampling clock. Instead of working with the simplified jitter value, frequency domain analysis preserves crucial application-specific frequency offset information and may be better suited for working with modern, high performance RF sampling converters.
Heterodyne receiver designers traditionally specify sampling clock requirements in terms of jitter. Clock jitter is calculated by integrating the clock source phase noise over a certain bandwidth. This process removes all frequency-dependent noise information. The passband of a bandpass filter on the clock input, or the bandwidth of the clock input to the analog-to-digital converter (ADC) itself, often determines the far integration limit. The jitter of clocking devices is often specified over a band from 12 kHz to 20 MHz offset, which originates from an older telecom synchronous optical network (SONET) classification and is reasonably close for most applications (equivalent to using a bandpass filter with a ~40 MHz passband). It also enables system designers to easily compare the jitter performance of different devices. Using this jitter specification in heterodyne receivers is usually acceptable, as most systems use moderate ADC clock rates (< 250 MSPS). External devices can also provide low phase noise clock signals (< 120 fs) to the data converter by internally dividing from a high frequency, low phase noise voltage-controlled oscillator (VCO).
When using time domain jitter, in theory, clock phase noise should be integrated over approximately 2x the clock input bandwidth.1 However, as designers develop radios using direct RF sampling converter, such as the TI ADC32RF45, a different method may be much more appropriate: focusing on clock phase noise in the frequency domain within the relevant band of interest and ignoring noise beyond that. For example, a system specification for a radar receiver or multicarrier GSM (MC-GSM) base station may state a minimum signal level at the antenna input (see Table 1) to provide accurate detection in the presence of an in-band interferer (a signal located within the passband of the filters in the signal chain). A typical example would be a radar receiver in the presence of a jammer or a cell phone tower trying to communicate with a cell phone at the edge of the coverage zone, while a different cell phone is transmitting at full power close by.
The receiver requirement may focus on only a small frequency spectrum within the 3GPP MC-GSM specification, 800 kHz offset from the blocker with a 200 kHz channel bandwidth, for example. There are several different noise contributors to consider, such as spurs and intermodulation distortion products caused by large interferers, thermal noise and clock noise. For the clock noise (see Figure 1), rather than trying to solve for a 6 GHz integration bandwidth when operating the RF ADC at 3 GSPS, it may be more accurate to simply figure out the clock noise contribution within the 200 kHz channel bandwidth of interest.
Clock Noise for Direct RF Sampling Receivers
When asked about phase noise requirements for RF sampling converters, the answer depends on the product specifications and several factors that impact the clock noise of data converters. These include:
ADC aperture jitter2—Aperture jitter is timing uncertainty inside of a data converter. During the sampling process, the external clock signal triggers the capture in the presence of noise. Ideally, this is flat noise in the frequency domain, but with low geometry CMOS converters, a 1/f noise component can be present.
Clock amplitude or slew rate—The ADC aperture jitter is quite sensitive to clock slew rate or amplitude, especially as input frequencies increase (see Figure 2). When using a sine wave clock signal, slew rate and amplitude are directly related to each other. The data converter signal-to-noise ratio (SNR) in the data sheet is typically characterized with a large clock signal (> 1.5 V peak-to-peak) for minimum aperture jitter degradation.
External clock phase noise—During the sampling process, both the external phase noise and ADC aperture jitter are modulated on top of the input signal. Spurs on the external clock are modulated onto the input signal as well.3 This is illustrated in Figure 3, where a 5 MHz-wide noise pedestal at a 6 MHz offset is added to the sampling clock. A close look at the fast Fourier transform (FFT) spectrum shows the same noise pedestal modulated to the input signal with a 6 MHz offset on either side.
Signal input frequency—ADC SNR degradation due to clock noise is directly affected by the frequency of the input signal. In the frequency domain noise analysis, the total clock noise is scaled by 20log (input frequency/clock frequency) during the sampling process. The higher the frequency of the input signal, the larger the clock noise contribution. System designers are well aware of this concept in the time domain, where the noise contribution due to jitter scales with input frequency is SNR = 20log(2π × FIN ×TJitter).4
Input signal amplitude—Clock noise gets modulated onto the input signal; hence, the lower its amplitude, the lower the actual modulated clock noise contribution. The automatic gain control loop in the receiver tries to maintain the input signal level close to the ADC’s full scale to maximize the signal chain gain. Adding some back-off reduces the risk of saturation but also reduces the noise degradation from clock noise. Figure 4 shows that the clock noise contribution improves directly when reducing the input signal amplitude.
ADC Noise Analysis
For a more accurate specification of the external sampling clock phase noise requirement at specific frequency offsets, follow these steps to analyze the data converter noise contribution in the frequency domain:5
1. Obtain the external clock phase noise and ADC aperture jitter in the frequency domain in decibels relative to the carrier frequency (dBc/Hz). The frequency bin sizes and frequency steps must be identical. Typically, the clock phase noise data is in a log-type format. If the ADC aperture jitter is not assumed flat across frequency, some data interpolation may be necessary to match the data format of the clock phase noise. As discussed earlier, the ADC aperture jitter is clock amplitude dependent, which needs to be considered.
2. For each frequency bin, combine the external clock phase noise and the ADC aperture jitter using Equation 1. This addition is illustrated in Figure 5.
3. Adjust the clock noise by accounting for the signal input frequency. The noise in each frequency bin is shifted by Equation 2
where FIN is the signal input frequency and FS is the ADC sampling rate. As the signal input frequency increases, SNR degradation due to clock noise increases as well.
4. Account for the amplitude of the input signal. The clock noise contribution is reduced when the signal amplitude is less than the ADC full scale. For example, a 3 dB back-off (Ain = -3 dBFS) reduces the noise power in each frequency bin by 3 dB.
5. Calculate the total ADC noise contribution by adding the ADC thermal noise. The last step is to combine the final clock noise with the inherent thermal noise of the data converter. This results in the expected total noise contribution from the ADC for specific frequency offsets from the input signal (see Figure 6).
This analysis matches typical observations. For example, as the signal input frequency increases, the clock noise increases by 20log(FIN/FS). Depending on the actual setup, the far-end noise floor increases above the ADC thermal noise, and a broad noise floor increase is observable (see Figure 4). Similarly, the clock noise contribution reduces as the input signal amplitude is decreased.
Calculation Versus Measurement
Using the aperture jitter profile information of the TI ADC32RF45, along with the phase noise information of both the clock and input signal generators, the total noise is calculated for a clock frequency of 3 GSPS with an input signal of 1.8 GHz at -1 dBFS amplitude. The result in Figure 7 shows a very close match, considering that other contributors such as power supply noise and temperature are not included.
- T. Neu, “Clock Jitter Analyzed in the Time Domain, Part 2,” Texas Instruments Analog Applications Journal (SLYT389), 4Q 2010.
- T. Neu, “How Unmatched Impedance at the Clock Input of an RF ADC Affects SNR and Jitter,” Texas Instruments Analog Applications Journal (SLYT679), 3Q 2016.
- T. Neu, “Impact of Sampling Clock Spurs on ADC Performance,” Texas Instruments Analog Applications Journal (SLYT338), 3Q 2009.
- R. Keller, “Signal Chain Basics #45: Is High-Speed ADC Clock Jitter Being Over-Specified for Communication Systems?” Planet Analog, September 2010.
- T. Neu, “Clocking the RF ADC: Should You Worry About Jitter or Phase Noise?” Texas Instruments Analog Applications Journal (SLYT705), 1Q 2017.