IDT Adds 1.8 V Dual-Channel Buffers to RF Timing Family
Integrated Device Technology (IDT) introduced four dual-channel fanout buffers for distributing high frequency clock and data signals. Targeting wireless infrastructure and other communications equipment, the 1.8 V low voltage differential signaling (LVDS) buffers add very low phase jitter, typically less than 45 fs. Each of the two independent channels provides up to eight low-skew outputs. Isolation between channels minimizes noise coupling, and AC characteristics such as propagation delay are matched between channels.
Operating at 1.8 V, the buffers have up to 50 percent lower power consumption than competitive devices, while maintaining clock performance. The power reduction allows higher system packing densities, saves cost in the power supply and cooling and delivers lower power footprints. The lower supply rails support deeper submicron silicon processes.
The devices enable two different signals to be buffered while remaining synchronous with one another; one channel can be used for a clock, the other for a synchronization signal or data, as applicable in device clock and SYSREF signal distribution in JESD204B applications.
“Relative to system timing distribution, RF designers no longer have to make power consumption trade-offs at the benefit of optimizing signal-to-noise ratio,” said Kris Rausch, general manager of timing products at IDT. “These new devices offer superb AC characteristics at a low 1.8 V power supply; a combination that assists designers in maintaining optimum signal-to-noise performance as well as lower power consumption and less heat dissipation.”
These latest members of the 8P34S buffer family join five previously introduced single-channel devices and are compatible in pin and function to equivalent industry standard 2.5 V and 3.3 V products from IDT.