Microwave Journal

Designing Next-Generation AESA Radar

November 14, 2016

Recent trends in active electronically scanned arrays (AESA) are targeting new radar payloads for satellites and unmanned aerial vehicles (UAV). These payloads, along with updated ground, airborne and shipborne radar, will help military planners meet changing operational requirements and the need for better situational awareness through improved intelligence, surveillance and reconnaissance (ISR) systems. These radar payloads are driving size and performance requirements, which are being addressed through novel architectures and system capabilities made possible through improvements in microwave and signal processing technologies such as GaN power amplifiers (PA), new monolithic microwave integrated circuits (MMIC) and “extreme” MMIC devices, heterogeneous “more than Moore” integration, cost reductions for transmit/receive (T/R) modules, new millimeter wave (mmWave) silicon ICs and electro-optic integration.1

Behind these development efforts are a host of evolving electronic design automation (EDA) technologies that support designers with system architecture, component specifications, physical design of individual components and verification prior to prototyping. This article will discuss these technology trends and present several examples where advances in EDA tools are supporting next-generation AESA and phased array radar development.


An AESA radar, also known as an active phased array radar (APAR), consists of individual radiating elements (antennas), each with a solid-state T/R module containing a low noise receiver, PA and digitally-controlled gain and phase (or delay) elements. Phase and amplitude control of the input signal to the individual elements provides steerable directivity of the antenna beam over both azimuth and elevation, which allows the radar to “aim” the main lobe of the antenna in the desired direction. Unlike a mechanically-steered radar, a phased array can rotate its pattern in space with practically no delay. Digital control of the module transmit/receive gain and timing permits the design of an antenna with beam steering agility, interleaving radar modes and extremely low sidelobes, which provides a significant reduction in antenna radar signature compared to passive electronically scanned arrays (ESA) and mechanically-steered antennas.2 The width of the beam depends on the number of elements in the array. By increasing the number of elements (or sensors), the beam becomes sharper and more efficient in detecting smaller size targets. Today’s AESA radars typically consist of thousands of individual elements, electrically interconnected through increasingly complex structures designed for reduced size and weight and better performance (in other words, lower loss).

Figure 1

Figure 1 AN/APG-80 F-16 AESA radar built by Northrop Grumman, showing partial view of the individual array elements.

At RF frequencies below 10 GHz, where a longer wavelength increases the antenna size and spacing, the RF, IF and baseband signal routing can be addressed with discrete components and off-the-shelf MMICs on printed circuit boards (PCB). The impact of longer traces will be offset by the lower PCB losses at these frequencies, and the interface to the antenna can be considered independent of the IC unit cell, due to the relatively flexible packaging requirements. However, at mmWave frequencies (i.e., above 30 GHz), physically short antenna spacings (~λ/2 < 5 mm), packaging losses and manufacturing challenges with impedance-controlled, multi-layer packaging interconnects make high functionality ICs and sophisticated integration more attractive. Designing these complex packaging schemes for high frequency signaling must be addressed with circuit simulation and electromagnetic analysis that is specialized for RF and microwave electronics.3

While actively steered phased array antennas have many advantages, they are extremely complex, and their nonrecurring development and production costs are significantly higher than a conventional antenna design. The higher development costs are driven by the inclusion of hundreds to thousands of active electronic modules per production unit (see Figure 1), often implemented with custom GaAs MMIC designs (typically 5 to 10 designs per system).


Initially funded and developed through U.S. Department of Defense (DoD) support in the 1980s and 1990s, GaAs MMIC technology was the only viable option for manufacturing the densely packed (cross section < 1 cm) T/R modules operating at 10 to 20 GHz. Advances in MMIC design have been enabled by the greater availability of powerful simulation software and inexpensive computing, which allows engineers to design increasingly complex circuits with greater accuracy and to develop libraries of frequently used RF building blocks. Where earlier MMIC development addressed the challenge of combining tens to hundreds of active and passive components (i.e., transistors, PIN diodes, resistors, capacitors and inductors on a single GaAs substrate), integrating AESA functionality scales in complexity when combining RF blocks such as low noise amplifiers (LNA), PAs,  and switching and phase shifters onto a single or multi-channel MMIC. Ever greater functionality and density are being developed through multi-chip modules (MCM) that utilize revolutionary materials, devices and advanced integration techniques.

Figure 2

Figure 2 110 GHz, 4×4 wafer-scale phased array transmitter.

The Defense Advanced Research Projects Agency (DARPA) Microsystems Technology Office sponsored two programs to investigate next-generation device integration. The DARPA Compound Semiconductor Materials on Silicon (COSMOS) program focused on developing new methods to tightly integrate compound semiconductor (III-V) technologies within state-of-the-art silicon CMOS circuits. The DARPA Diverse Accessible Heterogeneous Integration (DAHI) program continues this work by developing heterogeneous integration processes to intimately combine advanced III-V devices using emerging materials and devices with high density silicon CMOS.4

Integration technology has made significant advances over the past 10 years. In 2006, for the DARPA Integrated Sensor is Structure (ISIS) program, Georgia Tech Research Institute developed a four channel X-Band SiGe T/R module with the control circuitry on a single chip and a per-T/R module cost of ~$10. In 2008, researchers at the University of California San Diego (UCSD) achieved a huge leap in performance and integration density with the demonstration of the first SiGe RF-beamforming IC: a 6 to 18 GHz, 8-element phased array receiver with 5-bit phase control and an on-chip 8:1 combiner.5 In 2009, UCSD followed this with a demonstration of the first 16-element, 45 to 50 GHz phased array transmitter. By 2013, UCSD reported a 110 GHz, 4×4 wafer-scale phased array transmitter with high efficiency on-chip antennas,6 successfully demonstrating a single chip solution (see Figure 2).

While phased array antennas are evolving into silicon core chips that support multiple radiating elements, preferred solutions frequently combine silicon with III-V front-ends for applications that require the best possible performance, especially for figures of merit such as noise figure (NF) and output power. Increasingly, GaN is displacing GaAs as the material of choice for high power or broadband front ends. For a fixed power level, a GaN MMIC can be one third to one quarter the size of an equivalent power GaAs MMIC, a power density that is enough to offset the higher material cost of GaN compared to GaAs. While the finished GaN wafer (including material) costs twice that of GaAs, the resulting GaN solution is only 50 to 66 percent of the cost per RF watt generated with a GaAs solution. As the cost of GaN continues to decrease, the elimination of GaAs from phased antennas can be expected for many applications.7

Continued investment in wide bandgap (WBG) semiconductors is expected to take “more than Moore” power electronics to another level. Researchers are looking to enhance GaN technology by heterogeneously integrating GaN on top of silicon wafers. The integration of GaN onto larger silicon wafers and the use of standard semiconductor manufacturing processing will provide significant functionality and performance advantages at much lower cost. All these technology options require that designers have an efficient way to understand trade-offs between individual technologies and the impact on overall performance.

Even though the density of a GaAs MMIC is much lower than that of competitive silicon digital ICs, high frequency electronic design requires careful attention to interconnect technology and “EM aware” simulation that is able to predict the parasitic behavior that leads to performance failures. The physical arrangement or layout of components and interconnects is such a critical part of RF/microwave circuit design that software should utilize a unified data model (UDM) to inherently link schematic-based electrical elements to EM simulation-ready layout. This level of analysis is increasingly critical to successful MMIC development, as the technology and integration levels evolve.

While the integration of III-V and Si technologies addresses the size and functionality requirements of next-generation phased arrays, high density ICs also increase the need for wafer processing quality, since losing one transistor out of a hundred due to a fabrication defect amounts to losing the entire, costly die. As a result, the design of a complete microwave RF circuit on a chip requires established RF design rules for the layout of components and interconnections. Robust design, by way of yield/corner analysis, must also be incorporated into the design stage, to study the impact of manufacturing tolerances.


System engineering plays a key role in the convergence of silicon at mmWave frequencies. As the industry shifts toward highly integrated, feature-rich core chips, it is increasingly important that RFIC developers have in-house system expertise to fully examine the trade-offs in architecture and available technologies. System simulation that links circuit simulation to the analysis of radio and signal processing behavioral models enables the system designer to select the optimum monolithic process(es) for the application and perform early architecture definition and component specification.

One contributor to design failure and the resulting high cost of development is the inability of high level system tools to accurately model the interactions between the multitude of electrically interconnected channels that are separately specified. Constructing full or partial phased array systems to investigate these unforeseen interactions is also very expensive, because of the costs of fabrication and testing the interactions of hundreds to thousands of channels. This challenge will only increase with the continuing integration of the antenna array and beam steering control electronics.

Since fabrication and test iterations during design are cost prohibitive, development is typically limited to one prototype in a Phase I or Phase II proof-of-concept demonstration. Failure to meet the specifications leads to an unacceptable number of design and test iterations of the complete antenna/electronics system, making simulation that incorporates the entire system a necessity. Since phased array performance is not driven purely by the behavior of the antenna or microwave electronics, simulation must capture their combined interaction to accurately predict the overall system.

While EDA tools for individual circuit spaces are mature, the adoption of tools to evaluate the overall system performance as a function of combined subsystems is not as widespread. Often, the high level system analysis is performed using custom implementations by way of spreadsheets (e.g., Excel) or generic mathematical calculations using products such as MATLAB. Typically, these custom solutions vary in complexity from company to company, even among different projects within the same company. Such custom tools are generally used to specify the performance requirements of the underlying subsystems (i.e., MMICs, antennas, RF passives and control elements).

A more robust analysis combines the performance metrics of each of the subcomponents of a phased array system to provide a more accurate accounting of the high level system performance. Initially, the analysis is used to specify the overall system component topology and performance requirements of the individual subsystems. As more detailed models of the subsystems become available, these subsystem models and/or measurements can be integrated into the full system analysis to obtain a better understanding of the overall system performance.

System analysis enables designers to:

  • Evaluate array performance over a range of power levels and frequencies
  • Perform various budget analysis measurements, such as cascaded gain, NF, output power (e.g., P1dB), gain-to-noise temperature (G/T)
  • Evaluate sensitivity to imperfections and hardware impairments via yield analysis
  • Perform end-to-end system simulations using a complete model of the phased array.

Parametric analysis also allows the designer to efficiently study changes to the system to balance cost vs. performance. Examples of parametric studies are T/R module specifications, phase shift resolution (i.e., number of bits) and errors, combiner/divider topologies, resistive vs. reactive amplitude shaping, the number of antenna elements and antenna element spacing.


As an example of this approach, new capabilities for full system analysis of AESAs have been added to Visual System Simulator™ (VSS), the system level simulator that operates within the NI AWR Design Environment platform. The simulator provides full system performance as a function of steered beam direction, the antenna design and active and passive circuit elements used to implement the electronic beam steering. The current version of VSS enables modeling of phased arrays with thousands of antenna elements. It allows array configuration using various standards, as well as custom geometries. Previously, phased arrays were implemented using basic individual blocks, and their sizes were limited to several hundred elements, each modeled as a single input/single output block. Now, the phased array’s behavior can easily be defined through the parameter dialog box or a data file containing configuration parameters, such as gain and phase offset, θ/φ angles of incidence, X/Y location (either in absolute length or lambda) and signal frequency. The phased array model can be set to either transceiver (Tx) or receiver (Rx) mode. In Tx, the signal power exciting each element is calculated based on the signal setting defined by the user, including:

Figure 3

Figure 3 Gain and phase tapering used for beam shaping, steering and sidelobe control.

  • Lossless, which excites all array elements by the power of the input signal
  • Power divider, where the input signal is divided equally among all array elements
  • Voltage divider, where the input signal is divided equally among all array elements, such that the sum of their voltages equals the input signal.

Amplitude excitation through gain tapering is often used to control beam shape and reduce sidelobe levels. A number of commonly used gain tapers are implemented in the phased array block. Gain taper coefficient handling defines whether the gain taper is normalized; if it is, the taper is normalized to unit gain. Standard gain tapers in the phased array model include Dolph-Chebyshev, Taylor Hansen and uniform. The user can also define custom gain tapers by specifying the gains and phases for each array element (see Figure 3).

Along with various signal distribution schemes and support for frequency-dependent operation, the model allows users to simulate array imperfections caused by manufacturing flaws or element failure. All gain and phase calculations are performed internally, and yield analysis can be applied to the block to evaluate sensitivity to variances of any of the defining phased array parameters.

Figure 4

Figure 4 Lattice (a) and circular (b) phased array geometries.

The parameter dialog box enables the user to quickly define the antenna array architecture using standard or custom geometries. The lattice option (see Figure 4a) allows configuration of the phased array in a lattice pattern, which is configured using the number of elements along the X and Y axes (NX and NY), element spacing along these axes (dx and dy) and the angle between these axes (γ). Any positive value for γ may be used to configure the lattice. Setting γ to 90° results in a rectangular lattice, while γ= 60° creates a triangular lattice. The circular option (see Figure 4b) configures circular phased arrays with one or more concentric circles. The number of elements in each concentric circle and the radius of each circle can be defined as vectors by variables NC and R. Alternately, the user-defined option allows for custom array architectures using the number of array elements, N, and their X and Y locations.

Designers can define gains or full radiation patterns for each antenna element in the phased array. This allows them to use different radiation patterns for internal, edge and corner elements. The radiation pattern of each antenna element will often be affected by its position in the array. These patterns may be measured in the lab or calculated in an electromagnetic (EM) simulator such as AXIEM for planar EM and Analyst™ for 3D FEM analysis, simulators within NI AWR software. A simple approach is to use a 3 × 3 phased array and excite one element — the internal element, one of the edge elements or one of the corner elements — and terminate all others. This will provide the internal, edge and corner element radiation patterns, respectively, which can automatically be stored in data files using the NI AWR software output data file measurements. This approach includes the effect of mutual coupling from first-order neighbors. A 5 × 5 element array may be used to extend the mutual coupling to second-order neighbors.

Another new feature in VSS is the capability to model the RF links of individual elements in the phased array. This is an important functionality, since RF links are not ideal and can cause array behavior to deviate significantly from ideal. As an example, gain tapers are commonly used in phased arrays; however, using identical RF links for all antenna elements may cause certain elements (the ones with higher gain) to operate near or in compression, while the others will be linear. Array performance will be affected by how close to compression the elements operate. Alternatively, based on the gain tapers that are used, designers may choose different RF link designs for different elements. While this is more complicated, it results in more efficient phased arrays, and the VSS modeling allows designers to achieve this.


The capability to design and verify the performance of individual components, as well as the entire signal channel of an AESA radar, becomes a necessity as element counts and the integration of the antenna with the electronics increase. Using circuit simulation, system-level behavioral modeling and electromagnetic analysis within a single design platform enables development teams to investigate system performance and component-to-component interaction prior to costly prototyping. Being able to predict performance and modify the RF design so that requirements are met is one of the capabilities that modeling functionality of VSS offers.


  1. Thomas E. Kazior, “Beyond CMOS: Heterogeneous Integration of III–V Devices, RF MEMS and Other Dissimilar Materials/Devices with Si CMOS to Create Intelligent Microsystems,” www.ncbi.nlm.nih.gov/pmc/articles/PMC3928903/.
  2. Carlo Kopp, “Active Electronically Steered Arrays, A Maturing Technology,” www.ausairpower.net/aesa-intro.html.
  3. Xiaoxiong Gu et al., “W-Band Scalable Phased Arrays for Imaging and Communications,” IEEE Communications Magazine, Vol. 53, Issue 4, April 2015, pp. 196–204.
  4. Sanjay Raman et al., “The DARPA Diverse Accessible Heterogeneous Integration (DAHI) Program: Towards a Next-Generation Technology Platform for High-Performance Microsystems,” CS MANTECH Conference, April 23–26, 2012, Boston, Mass.
  5. “An Eight-Element 6 to 18 GHz SiGe BiCMOS RFIC Phased-Array Receiver,”  Microwave Journal, May 4, 2007, www.microwavejournal.com/articles/4757-an-eight-element-6-to-18-ghz-sige-bicmos-rfic-phased-array-receiver.
  6. “Researchers Develop First Silicon Wafer-Scale 110 GHz Phased Array Transmitter,” PhysOrg.com, April 6, 2012, www.phys.org/news/2012-04-silicon-wafer-scale-ghz-phased-array.html.
  7. Mike Harris et al., “GaN-Based Components for Transmit/Receive Modules in Active Electronically Scanned Arrays,” CS MANTECH Conference, May 13–16, 2013, New Orleans, La.