Another important goal of the cell layout was to keep the switching transients on the bias lines to a minimum so that switching times could also be minimized. This was accomplished by keeping the length of these lines as short as possible to reduce line parasitics. With the RF lines and supply decoupling on the top layer, the PA bias and LNA bias lines from the BFIC to the Tx/Rx module had to be routed on the PCB inner layers 4 and 5. The various digital control lines to the BFIC from the microcontroller were routed on Layer 5, which is shown in Figure 4 and Figure 5. On larger arrays with necessarily longer trace runs between the controller and BFICs and/or higher clock speeds, signal integrity simulations must be done to account for all trace propagation delays and ensure all digital timing is correctly synchronized.

Figure 4

Figure 4 Layer 4: PA bias, LNA bias and TR switch control routing (Layer 1 pins superimposed for reference).

Figure 5

Figure 5 Layer 5: LNA bias, TR switch control and digital routing (Layer 1 pins superimposed for reference).

On the Analog Devices planar phased array system board, the RFIO trace is short and immediately goes to a connector; thus, its isolation to other ports is high. However, on a real-world planar phased array application board, care must be taken when routing the Tx/Rx module antenna ports and the RFIO port, particularly the Channel 2 antenna and Channel 3 antenna ports shown in Figure 2 as they are on the same side of the cell layout as the RFIO port. While in transmit mode, the paths have higher gain relative to Rx mode and the isolation requirement between the paths is higher to prevent instability and oscillations.


In a planar phased array system with the antenna array on one side of the board and components on the other side, the heat sink must be located on the component side of the board. This presents a challenge for generating a thermal management solution that will effectively remove a sufficient amount of heat from the various components, particularly the PAs, so that none of the components exceeds its maximum junction temperature.

Options for Heat Management in a Planar Phased Array Antenna

Figure 6

Figure 6 Component side heat-sinking with an LFCSP package with heat flowing primarily through the bottom of the package (a). Component side heat sinking with a copper-pillar flip-chip LGA package with heat flowing through the top and bottom of the package (b).

Figure 7

Figure 7 A planar phased array front-end with component side heat sink.

With the antenna array’s location on the back side of the board, the thermal management solution cannot rely solely on the heat being pulled from a component’s ground paddles through thermal vias to a back side-mounted heat sink. Instead, the heat must flow directly from the top side of the component or it must travel indirectly through the base of the component into the PCB, moving laterally before coming back out to a component side heat sink. This is shown in Figure 6a and Figure 6b. There are two possible options for heat conduction away from the components:

  • The heat sink contacts large amounts of area of the top (component) side ground layer
  • The heat sink contacts the top side of the components.

The heat sink design largely depends on the power dissipation and thermal resistance values of the components. Most components have a low junction-to-case bottom thermal resistance (θJC-BOTTOM) and relatively high junction-to-case top thermal resistance. So, the scheme shown in Figure 6a is generally more effective.

The question becomes whether to additionally contact the top side of the components or not. If the junction-to-case top thermal resistance (θJC-TOP) is of the same order of magnitude as θJC-BOTTOM (for example, θJC-TOP < 5 × θJC-BOTTOM) having the heat sink also contact the top side of the component packages would provide an additional useful parallel path for heat conduction. The metal of the heat sink should not contact the top of the package directly as this may cause mechanical stress. Instead, a piece of thermally conductive tape or a thermal transfer pad should be used as shown in Figure 6b.

A real-world example of component side heat sinking of a planar phased array is shown in Figure 7. This is the same planar phased array front-end board shown in Figure 1, only with the heat sink attached. Thermal conducting compound can be seen at the interface between the heat sink and exposed ground metal on the board (the white material along the edge of the heat sink). Also, note the absence of fins in strategic areas to allow access to the RF input/output ports of the ADAR1000 BFICs.


Component side heat sinking forces each cell of the four Tx/Rx modules and one beamformer to be inside a metal cavity. Care should be taken in the sizing and design of the cavity. An electromagnetic simulation should be performed to ensure that the cavity does not interact with the circuitry and result in instability or oscillations. Analysis of metallic cavities whether for shielding purposes or thermal management cannot be overlooked at high frequencies. Resonant modes are generally supported when the largest cavity dimension is greater than or equal to λ/2 of the operating frequency in free space. Energy radiated from circuitry and PCB traces within the cavity have nowhere to propagate beyond the confines of the cavity, possibly resulting in instability and oscillatory behavior of active circuitry.

Various techniques can be employed to mitigate the undesired effects of cavity mode resonances. These techniques can be as complex as custom metallic structures within the cavity that only support resonances at frequencies outside the range of operation. A much simpler technique is the placement of an RF-absorbing material within the cavity to attenuate the energy of the resonant modes. The absorber is composed of materials that create a high permittivity and high permeability of the electric and magnetic fields, respectively, for a range of operational frequencies. This is analogous to an electrical bandstop filter.

The mechanical dimensions of the cavities in the Analog Devices planar phased array system board heat sink do support resonances at frequencies within its operational range. To mitigate the effects of the resonant modes, a die-cut RF absorber is installed within each cavity to dampen resonances without degrading the performance of the board. The RF absorber attenuation ranges from approximately 20 to 50 dB/cm over the frequency band of operation, effectively lowering the Q-factor of the cavity resonator.

Figure 8

Figure 8 Gain measurements before and after installing the RF absorber.

An electromagnetic simulation of the heat sink cavity and RF absorber was performed using Keysight’s EMPro simulation tool. A simple model was constructed to analyze a single cavity representing the mechanical design of the heat sink cavity, the PCB material and a bulk material to emulate the ICs attached to the PCB. Two simulations were performed using the finite element method simulation engine to calculate the eigenmode resonances within the cavity. The cavity material for the first simulation was defined as air and resulted in eigenmode resonances with high Q-factors. In the second simulation, RF absorber material was used as the cavity material instead of air and this resulted in no eigenmodes. The second simulation case concluded the selected absorber material lowered the Q-factor of the cavity suppressing the resonant energy within the cavity. To ensure accuracy, the two simulation cases were verified with measured data from the hardware. The frequencies that support resonant modes as well as the reduction of the Q-factor by the RF absorber can be observed in the two gain measurements shown in Figure 8. These before and after measurements confirm the simulated predictions and highlight the importance of electromagnetic analysis.


In this article, we have looked at the challenges associated with designing the RF front-end of a planar phased array system. The size restrictions that stem from the required lattice spacing at high frequencies demand novel approaches to circuit design. These challenges can be significantly reduced through the use of BFICs and Tx/Rx modules, which easily interface together. This glueless interface has the additional benefit of shorter RF traces and fewer control lines, resulting in systems with fast responses that are easier to calibrate. Because one side of the PCB is reserved for the patch antenna array, compromises must be made to implement an effective heat sink. Proper heat sink cavity analysis and design are also vital to avoid oscillations.