3D Smith Chart Tools S.R.L. has released a revolutionary and powerful learning, analysis and design tool for RF/microwave engineers: the 3D Smith Chart. The 3D Smith Chart is the first commercially available software tool that enables new capabilities for RF/microwave design that were not available using the original Smith chart, introduced in 1939.
Keysight GoldenGate is the best-in-class RFIC simulation tool inside the Cadence Virtuoso design environment. For many years, RF designers have relied on GoldenGate to solve their challenging problems and have benefited from its robust simulation convergence and fast simulation capabilities to fully characterize their transceiver designs prior to tape-out.
Ranging from mid-March to mid-June, interesting and informative webinars have been assembled. Diverse area of topics will be covered. The webinars will be presented by our knowledgeable team of engineers at FEKO and hosted through 'GoToWebinar'.
This NI AWR Design Environment(TM) white paper describes co-simulation capabilities of Visual System Simulator(TM) (VSS) system design software and LabVIEW, enabling system designers to better analyze, optimize, and verify complex RF systems inclusive of digital signal processing (DSP) blocks.
RF record and playback is an important method used to validate real-world GNSS (GPS, Galileo, GLONASS, and Beidou) systems. The sheer volume of data that these systems create necessitates being able to stream data to disk and analyze it later. Engineers and researchers are now recording and playing back real-world signals for all types of RF systems. They are simple to install and use and can be driven around in a vehicleâ??s trunk or backseat. These devices can record data including the exact location of a vehicle when important situations occur and precise weather and road conditions.
Miniaturization of consumer products, aerospace and defense systems, medical devices, and LED arrays has spawned the development of a technology known as the multi-chip module (MCM), which combines multiple integrated circuits (ICs), semiconductors dies, and other discrete components within a unifying substrate for use as a single component. This two-part white paper outlines the steps for implementing an integrated design flow within the AWR Microwave OfficeÂ® design environment for MMICs, MCMs and modules.Â Design flow considerations for both a GaAs PHEMT power amplifier design as well as for an MCM microwave monolithic integrated circuit (MMIC) design on a microwave laminate module are discussed.Â
The evolution of integrated circuit technology demands that designers in this field adapt to ever-changing manufacturing techniques driven by performance, cost, benefit, and risk demands. Today’s power amplifier (PA) designer working in solid state technologies must navigate a plethora of available processes, including gallium arsenide (GaAs), gallium nitride (GaN) and silicon carbide (SiC) pseudomorphic high electron mobility transistor (PHEMT), radio-frequency complementary metal oxide semiconductor (RF CMOS), and GaAs or silicon germanium (SiGe) heterojunction bipolar transistor (HBT), to name just a few. Similarly, different design challenges demand different amplifier classes and/or topologies like Class AB, Darlingtons, switch-mode PAs, and digital predistortion.
Traditional modeling methods such as rules of thumb and spreadsheet calculations (Friis equations) give limited insight on the full performance of an RF link in next-generation wireless products. This white paper highlights the advantages of using specialized RF system simulation software to accurately predict critical metrics for wireless RF links.
Optimizing a PA design for one parameter invariably requires sacrifi cing the
performance of another. This delicate balance between performance and
effi ciency is not the only conundrum, because designers of 4G PAs must also
contend with demands for greater instantaneous bandwidth. As a result,
designers of next-generation PAs are relying on simulation more than ever
before, and their tasks include frequency domain simulation, time domain
simulation, and now circuit envelope simulation.