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Envelope Tracking Simulation and Analysis

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12/13/12 1:00 pm to 12/13/12 2:00 pm EST

Agilent EDA 468x98 13dec12

 

Innovations in EDA Webcast

Title:
RF PA Design Series P5: Envelope Tracking Simulation and Analysis

Date:
December 13, 2012

Time:
10:00 AM PT/ 1:00 PM ET/ 6:00 PM UTC

Why this webcast is important:
Modern modulated signals have high peak-to-average power ratios (PAPR.) Power amplifiers that must amplify these high PAPR signals, if using a fixed bias, must be operated at relatively high output power back off, to avoid greatly distorting the signal when its envelope excursion is near its peak. However, the greater the amount of back off, the lower the efficiency of the power amplifier will be. Envelope tracking is a way of overcoming this issue, by allowing the amplifier's drain bias to track the magnitude of the input signal envelope. When the input signal envelope is low, the drain bias can be reduced so the amplifier operates closer to its optimal efficiency point. This webcast will provide an overview of Envelope Tracking simulation and analysis.

Topics will include:

  • What is Envelope Tracking?
  • Characterizing the power amplifier: Gain, gain compression, and PAE versus output power; Checking for memory effects
  • Simulating an ideal ET system – several different approaches: Examining the statistics of the modulated RF signal; Determining specification-compliant EVM for system/circuit co-simulation; Viewing results with the Vector Signal Analyzer software
  • Comparing performances with different gain-shaping tables
  • Modeling the effects of finite slew rate in the bias modulator
  • Modeling the effects of a time delay between the modulated RF input and envelope tracking bias signals

Who should attend:
Power Amplifier Designers

Presenters:
Steven Baker, Founder & Director, openET Alliance
Steven Baker has more than 15 years’ experience in international business development, marketing and strategy roles, building products and businesses in the mobile communications sector. He has particular experience in semiconductor and software IP licensing, working with digital and RF silicon vendors, software vendors, OEMs, ODMs and network operators right across the complex cellular ecosystem. A Chartered Engineer, he started his career with Marconi and holds a masters degree in Electronic Engineering from the University of Bradford.

Andy Howard, Agilent EEsof Senior Applications Expert
Andy Howard joined HP in 1985 as a development engineer designing microwave circuits. He spent a year in Japan as a systems engineer before becoming an HP EEsof applications engineer in 1993. His applications work has included simulating noise in nonlinear circuits, high-yield design techniques (design of experiments), Circuit Envelope applications, and for the past fourteen years Agilent ADS, RFDE, and GoldenGate examples. He developed the ADS Amplifier DesignGuide, and also worked on the Mixer DesignGuide. He has extensively updated the ADS Load Pull DesignGuide. He designed a high-speed prescaler IC using Agilent’s RFIC Dynamic Link, that was fabricated using IBM’s SiGe process. He is the author of the RFIC Flow Workshop. He graduated from U.C. Berkeley, B.S. E.E., 1983, and M.S. E.E., 1985. He was a visiting researcher for one year at NEC’s Central Research Labs in Japan while a graduate student, and is fluent in Japanese. He has published more than 20 magazine articles, HP or Agilent seminar papers, and application notes.

Open ET Alliance

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