- Buyers Guide
Title: Chip/Package/Board: Constraint Driven Co–Design
Date: December 6th, 2012
Time: 8am PT, 11am ET, 5pm CET
Memory interfaces have single-ended data rates in the 1GHz-plus range and serial links are running upwards of 10 gigabits per second. A precise analysis of each of these signals is required at silicon, package and board levels. The design and optimization performed on each one of these interconnection levels must be done in a global context.
This webinar proposes a global methodology which combines three dimensional (3D) electromagnetic (EM) analysis for PCB and package with chip power switching macro-modeling. Differences between a segmentation approach (where silicon, package and PCB are analyzed separately and then combined with standard cascading technique) and an integrated/global approach (where chip, package and PCB are analyzed as single entity in a co-simulation mode) are discussed, and based on the results, guidelines are outlined.
Antonio Ciccomancini Scogna, EDA Market Development Manager, CST of America
Antonio Ciccomancini Scogna received the PhD degree in Electrical Engineering from University of L’Aquila, Italy. He is currently EDA Market Development Manager at CST of America, Framingham, MA. His research interests include EM numerical modeling, printed and integrated circuits, packaging, and SI and PI analysis in high-speed digital systems. He has authored more than 70 publications and serves as reviewer for many international journals.