CST Webinar Series 2017
Providing a clean power supply voltage is a crucial element of PCB and Package layout design. Therefore designers rely on high fidelity simulation during the layout and verification stage. The impact of a noisy power supply on signal integrity can be considered in a circuit simulation using power aware IBIS or transistor level SPICE models of the transmitters and receivers. For the channel, however, often approximations are made as models for the power delivery network (PDN) and the signal nets are extracted separately.
This separate extraction neglects the effects of coupling between the power-, ground- and signal nets. We therefore propose a more rigorous approach where only a single model for the channel is extracted that includes both the signal nets as well as the PDN, therefore allowing a SI/PI co-simulation with unprecedented accuracy.
Using the example of a DDR4 memory interface we will demonstrate the additional signal impairment that is created by dual reference routing (Ground – Signal – Power) as well as voids in the reference planes and that cannot be predicted reliably using conventional extraction methods.
Because problems with reference planes are notoriously difficult to be considered in conventional 2.5D simulations, we will use a full 3D electromagnetic simulation of a test board and package to compute the S-Parameters of the channel, which includes the signal nets as well as the power and ground nets. A macro-model extraction tool will generate an equivalent circuit model that can be used in a circuit simulation.
As the circuit model will carry both the DC component of the power supply as well as the high frequency signal and high frequency noises, we will have to establish a workflow that ensures accurate performance of the model at very low as well as high frequencies. This poses challenges regarding the material modelling, frequency sampling, as well as decoupling capacitor modelling.
In this webinar we will present a novel workflow that starts from a Package and PCB layout and yields a high fidelity circuit simulation with signal integrity and power integrity being considered concurrently in the same model. We will give guidelines on what material models should to be used and how to extract an equivalent circuit model that is reliable from DC up to multiple GHz. We will develop these guidelines on a test vehicle before applying them to a real-world model of a DDR4 memory channel that is represented by a 3D model of the Package as well as the system board. As our workflow supports both IBIS and transistor level simulation flows, it is useful to both chip designers as well as system integrators.
Zhao Tong received his B.Eng. and M.Sc. in Electrical Engineering from National University of Singapore (NUS) in 2014 and 2017. In 2014, he started as a RF hardware design engineer at Marvell Asia Pte Ltd, Singapore, where he carried out 3D EM modelling, system level simulations, chip/PCB characterizations and EDA tools evaluation. Since early 2017, he joins CST SEA, Singapore as an Application Engineer and now focuses on 3D modelling and simulation of EDA and RF.