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Design and Characterization of SerDes Channels

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When

10/19/17 11:00 am to 10/19/17 12:00 pm EST

Event Description

CST 468x60

CST Webinar Series 2017

High Speed Channel Design typically involves two stages. In the pre-layout stage, the design space is explored through what-if analysis. In the post-layout stage the functionality is verified before a prototype can be manufactured.

In both stages realistic transmitter and receiver models including jitter, modulation and equalization need to be considered.

This presentation will highlight the key features for SerDes Channel Design in CST STUDIO SUITE including the new eye diagram tool.

Presenter bio:

Dr. Klaus Krohne received his electrical engineering degree (Dipl.-Ing.) from the Darmstadt University of Technology in Germany in 2001 and is PhD Degree (Dr. sc.) from the Swiss Federal Institute of Technology in Zurich in 2007. From 2007 to 2009 he worked as a research fellow at the A*STAR Institute of High Performance Computing in Singapore. His research interests include the development of simulation codes for electromagnetic fields as well as device optimization. He is currently with CST - Computer Simulation Technology as Market Development Manager for EDA based in Singapore.