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Passive channels pose significant challenges to serial link transmission for single-ended buses running at very high speeds. With the combined increase in data rates and routing density, crosstalk has become a major source of noise in current PCB designs. Reduced bit-to-bit, bytelane-to-bytelane and channel-to-channel spacing makes timing/voltage active margin analysis more challenging especially for single-ended and bidirectional buses. For this reason, simulating a full pad-to-pad link is becoming increasingly desirable. Being able to identify worst case lanes quickly and quantify crosstalk impact is crucial. Such an approach is still very challenging, especially for complex systems where the location and nature of aggressor signals change when moving from one component (package, board and connector) to the next.
This webinar will cover different aspects of the challenges in high-speed link modeling including chips, packages, PCBs, connectors and their interactions. A real-world high-speed memory bus test vehicle developed by Intel will be used for the correlation study. Full-wave electromagnetic modeling of the complete 3D link as well as a hybrid 2D/3D link modeling approach will be demonstrated and correlation for both passive (TDR/VNA) and active (system margins) measurements will be presented. The impact on system-level performance is analyzed by comparing results with and without crosstalk from adjacent lanes.
Darryl Kostka received the B.Eng. and M.Eng. degrees in Electrical Engineering from Carleton University, Ottawa, Canada in 2006 and McGill University, Montreal, Canada in 2009 respectively. He currently works as an Application Engineer at CST of America in the San Francisco Bay Area where he is involved in the signal integrity and power integrity analysis of high-speed digital systems including electromagnetic compatibility and interference modeling.
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