Pat Hindle, MWJ Editor
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Hindle
Pat Hindle is responsible for editorial content, article review and special industry reporting for Microwave Journal magazine and its web site in addition to social media and special digital projects. Prior to joining the Journal, Mr. Hindle held various technical and marketing positions throughout New England, including Marketing Communications Manager at M/A-COM (Tyco Electronics), Product/QA Manager at Alpha Industries (Skyworks), Program Manager at Raytheon and Project Manager/Quality Engineer at MIT. Mr. Hindle graduated from Northeastern University - Graduate School of Business Administration and holds a BS degree from Cornell University in Materials Science Engineering.

Commercial AESA Core Chips Hit the Market

September 22, 2015

Active Electronically Scanned Array (AESA) radar architectures have been in development for many years in military applications and now most military radar systems are using AESAs (where they make sense for the application). While transmit/receive modules for AESAs used to be made up of about 5 or 6 separate chips to perform all of the functions, highly integrated “core” chips, that perform most of the switch, attenuation and phase control functions, have been developed that can reduce the chip set down to just two chips or less as some core chips can control multiple array elements making the chip count less than two per transmit/receive path.

Highly integrated core chips are now being designed for broader use as AESA radar systems proliferate; and commercial radar, satellite and communication systems look to utilize this technology. One big potential for AESAs is 5G cellular systems that are projected to utilize this architecture to steer individual beams of RF energy more efficiently and reduce interference.

Two examples of companies commercializing this technology with the recent announcements of core chip technology are Peregrine Semiconductor and Anokiwave. They both use highly integrated Si technology to pack all of the functions into a single chip. Last week Peregrine released more information about their intelligent integration road map that has enabled them to develop its family of MPAC products (monolithic phase and amplitude controllers) for the LTE and LTE-A wireless infrastructure transceiver market. MPAC products provide phase and amplitude tuning flexibility in dual-path dynamically load-modulated amplifier architectures, such as Doherty amplifiers. Each controller integrates a 90-degree hybrid splitter, phase shifters, digital step attenuator and a digital serial interface on a single die. Building on the success of the MPAC product family, they are developing a family of core chips—monolithic controllers that offer phase and amplitude at microwave frequencies. Well suited for high density, compact arrays, these core chips provide a reliable solution to applications ranging from 5G beamforming to weather radar and air traffic control.

UltraCMOS technology and intelligent integration from Peregrine allow memory elements to be added to the chip that allow pre-loading of configurations. These configurations can then be automatically cycled at high speed. Additionally, integrated digital components allow flexibility to tune gain and phase at very fine resolutions. Peregrine’s architecture allows extra fill-in bits to increase resolution and results in a very broadband architecture.

Also last week, Anokiwave announced their first in a family of X-Band Silicon Radar Quad Core IC solutions for commercial radar and 5G communications markets. The AWS-0103 supports 4 radiating elements with dual beam Rx, single beam Tx, and includes 6-bit phase and 6-bit gain control. The part provides high input linearity in Rx mode and is intended to be used with a GaAs or GaN front-end chip. Additional features not found in many other core chips include gain compensation over temperature, temperature reporting, forward power telemetry with programmable delay power sampling, and fast beam switching using on-chip beam weight storage registers that can be accessed via direct address lines. Silicon technology enables very high integration of functionality thus enabling planar antenna design at X-band with reduced system size, weight and cost.

The Anokiwave device is a highly integrated TDD (time-division duplex) transmit-receive chip in a commercial QFN style surface mount plastic package with dimensions of 7 x 7 x 0.9 mm, easily fitting within the typical 15 mm lattice spacing at 10 GHz. The IC is controlled though a 5-wire serial to parallel interface (SPI) bus. They offer innovator kits and evaluation kits to customers for early access to the technology. The kits include boards with the AWS-0103 device, USB-SPI Interface module with drivers, and all required cables. Full production begins in January, with production-ready devices available June, 2016. Look for a thorough technical article on this technology in our November supplement focusing on 5G and IoT.

We expect a lot of future activity in the area of core chips and also the transmit front ends as commercial radar and satellite applications utilize this technology and 5G research increases to realize AESA solutions for future cellular communications systems. We will continue to publish heavily in this area following this trend.

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