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Leonard Pelletier is the Application Support Manager for Freescale RF in Tempe, AZ and is in charge of providing technical assistance to the amplifier design community. He has been with the company since 1995 working in this position supporting any and all RF applications. Prior to his work with RF components, Mr. Pelletier held amplifier design engineering positions with both the Motorola Cellular Infrastructure Group in Arlington Heights, IL and the Motorola RF Products Division in Torrance, CA
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In the RF LDMOS semiconductor business, everything is constantly changing. The applications change, the device requirements change, the customer’s expectations change and of course, the competition changes.
The latest applications change in the LDMOS market space is one of improved ruggedness and how to properly define and test the device’s new ruggedness criteria. In the ancient chronicles of past LDMOS history, we always talked about the standard universal test of applying a constant input CW test signal, of a high power level and maybe even an elevated VDD, then operating the device into a relatively nasty, high VSWR load test condition at all load phase angles to see if we could cause an electrical overstress event and damage the parts.
The all phase angle requirement was there to insure that the parts experienced both the high current stress of a low impedance load and the high voltage swings of a high impedance VSWR event. High current would stress the thermal design and high voltage would stress the voltage breakdown limits.
The problem was that this VSWR test did not really match the ruggedness requirements of the field applications. Yes, they simulated open circuit cables or ice covered antennas, but with modern LDMOS devices, the typical worst case range of these tests were of such a low stress level that they did not produce any failures in the course of normal operation.
With the new Doherty applications, we were starting to see occasional failures in the peaking amp device side, even though that device, in theory, had the lesser stress of the two sides, as defined by the standard VSWR criteria. It turned out that those devices were failing not due to thermal or standard, steady state DC voltage breakdown issues, but due to dV/dT induced snapback failures due to the rapidly changing nature of the peaking signal.
Investigations into the fast rise time snapback ratings of the various generations of LDMOS showed that there was very poor correlation between VSWR ruggedness and snapback ruggedness ratings.
Fortunately, we were able to change some of the internal design optimizations of our latest LDMOS structures and significantly improve their snapback ratings, both in a peak voltage level and in a peak current-to-failure rating.
So we will end this blog with a new rule of thumb for dV/dT induced snapback ruggedness ratings:
All 50V and 900 MHz HV8 devices are good for pulse rise times as short as 10 nSec. All other devices are limited to greater than 100 nSec.
This rule will change as more devices are rolled out in the future, but for the next 6 months, this will remain a valid assumption…
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