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RF Leonard Pelletier
Innovate or Die: Next Gen LDMOS Process Improvements
Leonard Pelletier is the Application Support Manager for Freescale RF in Tempe, AZ and is in charge of providing technical assistance to the amplifier design community. He has been with the company since 1995 working in this position supporting any and all RF applications. Prior to his work with RF components, Mr. Pelletier held amplifier design engineering positions with both the Motorola Cellular Infrastructure Group in Arlington Heights, IL and the Motorola RF Products Division in Torrance, CA
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In the semiconductor business, everyone is constantly revitalizing their portfolio, improving on the capability of their devices to make the next generation of parts significantly better than what is available now. Run faster, jump higher, PF flyers. The semiconductor business model is “innovate or die”. Either you are moving forward and winning or you are not-so-slowly dying. Competition drives the requirement for innovations and the fastest innovators typically have the best products, broadest portfolio base and the largest market share.
LDMOS is no stranger to this innovation requirement, and given that it takes, on average, about 18 months to create a new generation product platform, then it is high time we start seeing the 8th generation (HV8) series of devices start rolling out of the factory.
HV8 is different. You may have heard this before with previous generations and in this case, it is also true. The requirement for improved efficiency is always one of the main drivers for innovation, but the way HV8 achieves this goal is different from past generations of devices. Most of the HV8 improvements came about by reconfiguring the active channel, drain extension region of the LDMOS structure. Here, by altering the doping levels and controlling the electric field intensity, we can optimize the impact ionization potential. In this case, lower is better and lower impact ionization levels translate to a device with significantly improved ruggedness and lower hot carrier injection, which in turn reduces Vgs drift.
This channel optimization, along with some alternative top metal changes produces a generation of devices that have a 20% higher power density, on a watts per mm basis. A 20% improvement in power density translates to higher terminal impedances, wider bandwidth capability and 5 points higher efficiency at the P1dB compression level.
In addition to power and efficiency improvements, HV8 devices also have improved raw and DPD correctable linearity, which is the result of a 30% - 50% reduction in AM/PM phase distortion levels compared to HV7 devices. The efficiency and linearity improvements combine to create a device with significantly better performance in both traditional Class AB and Doherty amplifier configurations.
So it is innovate or die, and the improvements of HV8 show that LDMOS is not planning on pushing up daises anytime soon.
RF Leonard – follow me at www.twitter.com/RFLeonard
#IMS2009 - Coming up next: A New Test for Ruggedness: Fast Rising dV/dT