You know what amazes me? Design software. Agilent, AWR, Mentor Graphics, Ansys, Zuken…all of them amaze me! The power, the flexibility and the add-on tools that I often read about are truly stunning. Of course, not being a designer or engineer I am relatively easy to impress. Yet I do remember the design tools of old, and they didn’t contain a fraction of the power and features today’s tools offer. I am also amazed by the people who so deftly use these tools to design PCBs. These designers lay out boards that would have seemed like science fiction just a decade or two ago.
Recently, I was working with an engineer who had created a High Performance board that was complex—to say the least. In addition to over a dozen layers, it also contained buried and blind vias, filled vias, mixed dielectrics and multiple cavities—the whole shebang. Needless to say, once I quoted this design-marvel, he suffered a bit of “sticker-shock” when he saw the price. Luckily, he had the rare luxury of time, so he asked us about changes he might make to the design to help bring the price down. In this case, this was an individual who was wearing two hats, one as electrical engineer and one as board designer.
What I came to realize was that he had designed this board on a very powerful design platform and that some of the design features that made this board expensive to manufacture, were not really necessary. His primary training was in electrical engineering, after all, not in board design (or manufacturing). The powerful tools he was using allowed him to do some completely functional (however impractical) things in his design. Luckily, we were able to let him know what the major cost-drivers were so he could modify his design accordingly—which helped him to lower the board cost.
Because of this experience, I thought there may be more of you multiple-hat-wearing-engineering-types out there that may want to know what some of the key cost-drivers are for printed circuit board manufacturing as well. So, here you go!
- Layer count: The first, and most obvious, is layer count. More dielectric material, more imaging, more etching, more plating, will all obviously increase the cost.
- Base Laminate: Laminates required for RF/MW or any high performance board can range wildly depending on the needs of the performance you require.
- Copper Weight: Whenever the finished copper weight exceeds 1 ounce, cost will rise as the copper weight rises. In addition the etch factor becomes much more critical and challenging to control.
- Board size: For obvious reasons, the larger the board, the greater the cost.
- Buried and Blind vias: Every time you add buried and blind vias you increase the number of lamination cycles, drill operations, de-smear and plating operations—all of which drive costs up.
- Sequential lamination: Required when buried and blind vias are present. Sequential lamination increases labor and prep time as multiple lamination cycles must be done for each board.
- Multiple Drill Operations: Also necessary when using buried and blind vias. More labor and drill operations=increased costs
- Hole density: This can be per board or per panel. The more holes and variety of hole sizes--the longer the drills must be active and drill bits must be monitored and changed accordingly. Drill bit life is monitored carefully by the drill programs. After so many hits—the drill will stop and the bit must be changed to ensure clean hole-drilling which allows for even plating to follow.
- Very small features and tolerances: Requires extra oversight and careful process control. Upgraded entry and back-up drill material to ensure against things like “drill-wander” and over or under-etching. Laser drilling may be necessary which also adds cost, especially if the fabricator does not have laser drills in-house.
- Non-conductive Via filling:When filling vias, not only do the via holes need to be filled, but they must be cured properly and then planarized. Obviously, adding three more operations will add cost.
- Conductive via filling: Conductive via-filling is much more costly than non-conductive via filling. There are tiny particles of conductive material present (which costs more), then it must be cured and planarized as well. Note: It is not recommended to fill a via under 8-10 mils with conductive epoxy due to the size of the conductive particles.
- Edge plating: Plating edges requires extra processing steps and a little bit of black magic which adds to the cost.
- No X-outs allowed: When building and shipping PCBs (multiple up) in panel form, some customers require that every board in the panel be a good board, with no X-outs allowed for defective boards. This forces the board supplier to run more panels in order to get the required yield to fulfill the customer’s order. This cost gets passed on.
I hope this has been helpful. I’m certain that this is old news for many of you, but based on my recent experience, I thought this may be useful for some of those who find themselves wearing too many hats!
As always, I welcome your questions and comments.
Please come by and say “hello” at IMS if you are planning on attending the show. I will be in the Transline Technology booth #1706. Hope to see you in Seattle!