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AWR announced Version 2009 of its Analog Office high-frequency analog and RFIC design software. This latest release includes AWR’s patent-pending multi-rate harmonic balance (MRHB™) technology, which dramatically increases the speed and reduces the computer memory required to perform steady-state analysis of complex multi-tone designs such as those found in receivers and transmitters with multiple stages of up-conversion and down-conversion.
The challenge for software developers working in this arena has always been to provide the efficiency of simulating the passive portions of the circuit in the frequency domain while addressing the active devices in the time domain. Harmonic Balance, the circuit simulation technology of choice for time/frequency domain analysis, does this by dividing networks into its passive and active sub-networks and addressing the time/frequency interface with fast Fourier transforms (FFT); the more active devices in the network, the more interfaces, which results in a slow down of the simulation time. In the case of an RFIC where transistor counts number in the hundreds to thousands, the number of mathematical operations becomes quite large and the problem is compounded by device nonlinearity and high spectral content.
Taisto Tinttunen, chief director of engineering of AWR's APLAC division, explained the limitation of previous tools and the significance of MRHB: "Harmonic-balance engines traditionally do not scale well as the number of tones increases, so simulating a complete receiver or high-speed digital circuit was extremely difficult or impossible because of the high computational cost of nonlinear model evaluations and the extensive memory utilization."
"MRHB eliminates this limitation by defining harmonic balance analysis on a block-by-block basis, reducing filtered sources and their harmonics by defining new hybrid tones based on linear combinations of the source tones," he continued. "As a result, AWR's MRHB technology makes it possible to simulate designs that were previously beyond the reach of the harmonic balance technique, and provides a 5x speed increase when simulating large, complex multi-tone designs."
Multi-Rate Harmonic Balance (MRHB) is available for the Aplac harmonic balance engine only. MRHB is a technique of controlling what frequencies are simulated for each model in the circuit. For circuits with frequency conversion, this can significantly decrease the simulation time without loosing accuracy.
A simple up converter circuit can be used to demonstrate the basic concept of MRHB. Starting with the basic circuit below.
Where f1 is the tone set at the input port and f2 is the tone set at the LO of the mixer. With harmonic balance analysis, there are many mixing products from f1 and f2 at the output of the mixer. See the spectrum plot before for a sample spectrum at the output of the mixer.
For this example the amplifier at the output of the mixer is narrow band. See the amplifier response trace on the graph that shows the amplifier is matched at the f1+f2 signal and quickly attenuates the other frequencies. For traditional HB simulation, the amplifier at the output is solved for all the possible frequencies. For MRHB, the amplifier at the output is configured to only simulate at the dominate frequency. The picture below shows the spectrum at the output for the traditional harmonic balance analysis.
And the picture below shows the spectrum with MRHB.
Finally, the picture below shows the voltage waveforms at the output of the circuit.
In this simple example, there may not be too much time and memory savings from having the last amplifier use a limited set of frequencies. However, on circuits with several frequency translations, the item and memory savings is significant. See the examples in the AWRDE to see circuits that are significantly faster without a loss of accuracy when using MRHB.
Analog Office Version 2009 also offers AWR’s AXIEM™ 3D planar EM technology, which now supports 64-bit operating systems, multi-core PCs and shape pre-processing algorithms that decrease solution time for complex geometries.
Additional features in Analog Office Version 2009 include:
• Automated Circuit Extraction (ACE): Improved extraction flow using frequency-domain interconnect modeling technology along with more traditional RLCK extraction.
• Extract Flow with AXIEM: For very-high-frequency designs, the same layout can be effortlessly extracted to AXIEM software for full-wave 3D planar electromagnetic characterization.
• DRC/LVS: PowerDRC/LVS technology provides fast, accurate, affordable physical verification solutions for analog and mixed signal design and is now integrated into Analog Office software as an add-on module.
• OpenAccess: As a founding member of the Interoperable PDK Library (IPL) alliance, AWR supports open access (OA) process design kits (PDKs) and layout views that enable an interoperable design flow among EDA vendors.
• Sapphicon PDKs: Comprehensive PDKs are now available for Sapphicon Semiconductor’s advanced 0.25-µm RF complementary metal oxide semiconductor (RF CMOS) silicon-on-sapphire processes.
Version 2009 of Analog Office software is part of the AWR Design Environment (AWRDE™), which is now shipping to supported customers. For more information about Analog Office software, please visit www.awrcorp.com
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