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To enable wireless system on chip (SoC), RF transceivers and frequency synthesizers composed of RF/microwave blocks such as amplifiers and mixers along with additional functionality, such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and phase-locked loops (PLLs) must be implemented on the same process. At the same time, baseband circuits, microprocessors and memories are moving to the most advanced CMOS process node available. According to Tom Quan, Deputy Director of Design Service Marketing at TSMC, “65-nanometer process node enables designers to build single-chip wireless applications by integrating RF transceivers and synthesizers on to the same SoC with digital baseband and application processors."
The ever-increasing complexity of today’s RFIC design has led to continual advances in design automation, from circuit simulation techniques (improved capacity, speed and accuracy), modeling of parasitics (integrated electromagnetic simulation), manufacturing analysis (yield and sensitivity), to support for advanced measurements. Sophisticated software is required to address all these needs and most designers rely on a handful of specific tools to get the job done.
One of the many challenges in the design process is to accurately and efficiently predict the expected circuit and system performance. It is vital that the designer be able to perform silicon-accurate simulation and verify circuit and system performance using reliable simulations. RF designers also require sign-off accurate modeling of the substrate and RLCK extraction of interconnects to increase first-pass silicon success and reduce the cost of overall design.
The majority of RFIC design (circuit entry, simulation control, post-processing, physical design and verification) is conducted within Cadence’s Analog Design Environment, also known as Virtuoso, while circuit simulation is often addressed with some form of harmonic balance technique. Agilent Technologies, a provider of RF/microwave EDA, has announced the latest release of its RFIC simulation, verification and analysis software -- GoldenGate version 4.4, an advanced RF simulation and analysis solution for integrated Silicon-based mixed signal RFIC designs. GoldenGate performs both small and large signal analysis including DC, Transient, AC, Harmonic Balance, Noise, Envelope, Convolution and Envelope Verilog-AMS co-simulation; replacing RFDE as Agilent’s RF simulator in the Cadence Analog Design Environment (ADE) supporting both IC5 and IC6 releases.
The new release extends the products capabilities to address advanced node RFIC design with updates addressing:
• Enhanced performance for greater speed and capacity including a 2x improvement in speed for periodic steady state (harmonic balance) analysis
• New key stability and yield contributor analyses and RF extensions to mixed-signal simulation
• Improvements in Design Verification, including an enhanced System to IC verification flow for packaging wireless verification IP and fast envelope support for standards-based wireless virtual test benches
New Fast Yield Contributor Analysis
While statistical Monte-Carlo analysis for performance verification and yield has improved in recent years with the addition of advanced sampling techniques, boundary modes for corner analysis, etc., it has not proven to be a tool that designers use every day for circuit and block level design. The primary reasons are that for top level verification, standard statistical Monte-Carlo trials still take too long to complete and that results cannot easily give insight into what is causing the variability in the design. On the other hand, if relegated as a technique for final verification only, its potential impact on improving the performance yield is diminished.
In order to unlock the real potential of statistical Monte-Carlo at all phases of the RFIC design flow, Agilent has developed a new Monte-Carlo like analysis technique that is fast (50x), accurate, and that can determine the device, circuit, and block level contributors to performance variation in any phase of the design flow. Fast Yield Contributor analysis allows the designer to optimize at the circuit, block, and functional path level with an understanding of key underlying contributors and their correlation and statistical impact on overall performance. This fast and accurate yield analysis tool demonstrates good small-signal stastical agreement (1-sigma ) with regular Monte-Carlo, uses the same statistical PDK but requires only a single nominal simulation.
Figure 1.: Key Yield Contributors Plot
Figure 2: Comparison to Standard Monte-Carlo
This type of analysis is the missing link between normal circuit optimization, worse case analysis, and design for yield as it gives insight into stastical design sensitivity that can’t be obtained any other way. Agilent’s claim is that it accomplishes this by quickly identifying identifying the sources of variation and their impact on key product performances and specifications.
Periodic Steady State (Harmonic Balance) Based Stability Analysis The use of high Ft devices in advanced silicon and CMOS technology nodes for RFIC design can pose new problems related to circuit stability. While there are many techniques available to analyze the stability of RF circuits, most rely on DC, small-signal S-parameter analysis, or transient analysis to provide insight into potential oscillations. Many of these are small signal and can be performed relatively quickly. Transient analysis, however, the primary way to analyze large signal effects, can require long simulation times and complex and time consuming user interaction to determine the actual oscillation frequencies. To eliminate these barriers and provide a real tool for large signal stability analysis in advanced technology nodes, GoldenGate 4.40 introduces periodic steady state (Harmonic Balance) based Nyquist and Eigenvalue stability analyses. The large-signal black box stability of oscillators and driven RF and high speed circuits can now be analyzed under real signal conditions in a fraction of the time even for the largest circuits including parasitics. The nonlinear stability analysis identifies unwanted oscillations for even the largest circuits, operating many times faster than Transient techniques.
Figure 3: Harmonic Balance Large Signal Stability Correctly Identifies Single Oscillation Under Driven Conditions
Comprehensive Wireless Test Benches
Wireless communication systems continue getting more complicated with the release of each new standard. Systems engineers and RF IC designers need to collaborate more than ever on specifications driven verification. Agilent has leveraged the Ptolemy Systems Simulator and their comprehensive library of standards based wireless verification IP for RFIC design and verification in the Cadence Virtuoso based design flow. The approach allows the Systems Engineer to configure and package wireless verification test bench libraries for the RFIC Designer to use these in a manner appropriate for IC level design.
During the top-down design process, behavioral modeling will often be used to model each of the various functional blocks. To simulate system-level performance, one or more test benches must be created. In those test benches, the RF stimulus is generated and meaningful measurements can be extracted. The test bench may be used to simulate the entire RFIC and verify the performance against key wireless specifications like error vector magnitude (EVM) or adjacent-channel power ratio (ACPR). These initial simulations provide information about the expected ideal performance characteristics of the design. They also offer details of the design partitioning and requirements of the individual functional blocks.
Figure 4: GoldenGate Simulation with Wireless Verification IP
Figure 5: Typical Wireless Test Bench Outputs
These verification test bench libraries consist of the appropriate simulator settings, standards based or custom complex modulated RF or baseband sources, baseband algorithmic data processing sinks and Data Display visualization templates. There are over a dozen wireless verification IP libraries available covering cellular, mobile broadband, digital TV, and wireless video standards and their variants. Essentially, a wireless test bench is a collection of pre-configured parameterized sources, measurements, and post-processing setups. It is based on published specifications of a wireless standard, such as WLAN, 3GPP and TD-SCDMA.
Additional flexibility allows system architects to develop customized test benches early in the development cycle. Wireless test benches (WTB) give the RF-circuit designer a convenient means of verifying the RF circuit's performance against particular wireless standards. The underlying WTB simulation technology based upon the Agilent Ptolemy simulator has its roots in the University of California at Berkeley. Ptolemy provides the ability to model most of the blocks in a wireless system. It also offers the ability to simulate blocks at different levels of abstraction. These capabilities include the co-simulation of numeric signal-processing blocks with circuit-envelope and transistor-level circuit descriptions.
The RFIC designer can use these wireless verification test bench libraries as “Virtual Test Benches” in GoldenGate without modifying the designers golden schematic. Applications include any wireless design with RF to RF, RF to Baseband, Baseband to Baseband, or Baseband to RF signal configurations. This improved link between the RF Systems Engineer and RFIC Designer streamlines use of systems level verification IP during the RFIC design flow and lets each expert work in their own domain but still share vital information.
The resulting specifications for the functional RF blocks form the basis upon which the RF-circuit designer will develop the transistor-level implementation. Yet there is a danger to using this approach: The behavioral models employed may be underspecified. As a result, they may not always accurately predict the response of a real transistor circuit--particularly in the presence of a complex modulated RF signal.
Generally, the RF-circuit-block specifications that are derived from the top-down system analysis will be written in terms of circuit-performance parameters like gain, gain compression, noise figure, and so on. The RF-circuit design must be developed at the transistor level to provide adequate performance and satisfy these functional block specifications.
Several factors are key to the success of the RF-circuit design. Perhaps the most fundamental requirement is a set of device models that are silicon accurate and the use of a fast, accurate circuit simulator such as GoldenGate that is optimized for large RFIC CMOS designs along with new yield and stability analyses and standards-based verification test benches.