EDA Focus December 2009: Synopsys Pushes into RFICs
Synopsys Continues its Push into the RFIC Design Market. Expands Custom Design Portfolio with Unified Extraction Solution
In September of 2008, Synopsys introduced Custom Designer™ based on the Galaxy Platform to provide a unified solution for custom and digital designs. The custom IC design environment was built natively on the OpenAccess database, which in turn, supports legacy designs and interoperable process design kits (PDKs). According to Paul Lo, senior vice president and general manager of the analog/mixed-signal group at Synopsys, [the company’s] “vision is to deliver the industry’s most productive and open custom implementation solution.” Supporting legacy designs and foundry certified PDKs circumvents one of the major roadblocks to adopting new tools from a different software vendor - that is, the potential disruption from not using a company’s legacy design information. Another major roadblock is maintaining the look and feel that users expect from their software interface (what users like) while adding new capabilities and automation (getting rid of any frustrating features with their current tools).
This past July, Synopsys Inc. announced the availability of advanced analog simulation and layout capabilities in its Galaxy Custom Designer implementation tool. The new features in the 2009.06 release target analog circuit designers and layout engineers with new capabilities, including high-capacity, high-performance schematic-driven layout (SDL) designed for today’s large analog blocks. The SDL capability features robust schematic and layout synchronization technology and a streamlined engineering change order (ECO) flow. Also included in the 2009.06 release was an analog simulation and analysis environment featuring high-performance waveform display and processing, mixed text/schematic integration, and TCL scripting for batch verification. The release was previewed this past spring at the International Microwave Symposium (IMS) in Boston.
According to Ed Lechner, director of product marketing for analog and mixed-signal products, the overall goal is to increase productivity for custom designs in an open environment as process geometries shrink to 45 nm and below. Custom Designer offers time-saving analysis setup, run, save, and recall features; it provides hierarchical mixed text and schematic representations; and it supports cross-probe and schematic annotation with simulation results. He added that it forms the basis of a complete implementation, physical verification, circuit simulation, and analysis flow, integrating with HSPICE, Custom WaveView, Cadabra, IC Validator, StarRC Custom, and CustomSim, figure 1.
Figure 1. Synopsys Custom Design Solution
On the RF simulation side, HSPICE RF supports harmonic balance and shooting Newton techniques for analysis of weakly and strongly nonlinear devices, respectively. It also supports envelope analysis for complex modulated RF waveforms and S-parameter analysis for small-signal, linear components. He added that HSPICE RF can simulate more than 10,000 active devices in both harmonic balance and shooting Newton analyses. These capabilities clearly target the RFIC market where Cadence’s Virtuoso/SpectreRF and Agilent’s ADS/Golden Gate (environment/simulator) have been the dominant players for years.
Synopsys’s RF design capabilities now include design, analysis, modeling, and extraction tools as well as RF IP based on an RF flow using Custom Designer for schematic capture, HSpice RF for circuit simulation, Custom WaveView for analysis, Custom Designer for layout, IC Validator for design-rule checking, StarRC Custom for parasitic extraction, and CustomSim for verification. Other relevant tools, he said, include TCAD for device modeling, DesignWare IP (with blocks for applications such as FSK radios, GPS transceivers, mobile TV tuners, and UWB transceivers), the Sentaurus device-simulation tool (for multidimensional analysis), and Raphael (an interconnect field solver).
This past September, Synopsys, Inc. , continued its push into this market with the announcement of the StarRC™ Custom parasitic extraction solution for analog mixed-signal (AMS) and custom digital IC design. The company’s development team combined the Star-RCXT™ extraction technologies and environment with the Raphael™ NXT 3D fast field solver into a single, unified extraction solution. The resulting product offers high performance runtime with user selectable accuracy levels to meet the analysis demands of high-sensitivity custom circuits with features that include optimized links with Synopsys’ CustomSim™ circuit simulator (claiming a 10X boost in simulation runtime while preserving signoff-level accuracy) and seamless integration with Galaxy Custom Designer for enhanced designer productivity. Integration of StarRC Custom into the Synopsys Custom Designer cockpit, lets users set up extractions, run StarRC Custom, and explore the results directly from Custom Designer from either a netlist or physical layout circuit view.
Extracted Models and Circuit Simulation
StarRC Custom is intended for interactive design of custom blocks and for cell or IP characterization, emphasizing accuracy over capacity, while still offering reasonable extraction time and manageable simulation runs for custom IP and standard cell-sized problems. The product employs the Star-RCXT ScanBand engine, which is based on a table-driven algorithm. Synopsys claims this engine is capable of traversing 10 million nets overnight, extracting with 5 percent accuracy. StarRC Custom also integrates the Raphael NXT fast field solver engine, which is about three orders of magnitude slower but capable of far greater accuracy on structures that give problems to table-driven extractors. Such structures are increasingly showing up in the contact layer on 40-45nm processes, according to Robert Hoogenstryd, director of marketing for design analysis and sign-off tools at Synopsys. Some of these structures are so small that tiny absolute errors in parasitic capacitance are large percentage errors on low-impedance nodes. In the current version, the user selects whether the extraction will use ScanBand or Raphael NXT on a given structure.
New features in the extraction tool work directly with Synopsys's transistor-level simulator, CustomSim, to slash simulation times by reducing the complexity of the extracted models. While this capability is generally required for digital circuits, the benefit could also apply to analog designs.
Hoogenstryd cited three specific techniques that would benefit these designs. First, the tools could be applied to a back-of-the-envelope sensitivity analysis, where users could selectively retain certain device capacitances and remove parasitics from that do not significantly impact the net. For instance, a factor of eight reduction in simulation time was achieved by extracting only the device’s contact-to-gate parasitics and grounding all the other coupling capacitances and power net parasitics. This technique resulted in a two percent error in the calculated delay compared to the full simulation, but may be acceptable to the designer for the sake of speed.
An alternative method would attempt to increase simulation speed with less impact on accuracy by using activity files to identify the level of activity on each node, and to increase the level of extraction detail on the most active nodes while turning down the effort on the least-active ones. This can produce an order-of-magnitude speed-up in simulation, Hoogenstryd said. Finally, StarRC Custom provides the flexibility to use hierarchical or flattened design extraction. Simply employing hierarchy whenever possible can accelerate simulation a lot, but it can also introduce errors when different instances of the same structure are not, in fact, in equivalent contexts, and will have different parasitics. So StarRC Custom and CustomSim combination use effective technique to provide maximum back-annotation of the detailed flat parasitics while preserving the design hierarchy. The result Synopsys claims is a significant factor speed-up in simulation with minimal impact on accuracy. The three use models are shown graphically in figure 2.
Figure 2. Optimized Link with CustomSim. Extraction Tuned for High-Efficiency
The StarRC Custom solution allows custom IC designers to benefit from Star-RCXT’s existing qualification for 65-nm and 45-nm process nodes where Star-RCXT is already in use by more than 40 leading semiconductor companies at 45-nm and has been used on more than 140 tapeouts at 16 foundries. StarRC Custom was initially available to limited customers but is expected to be available to the general public in December.
“The widespread use of custom circuits in today’s complex system-on-chip (SoC) designs is creating a severe simulation and signoff bottleneck,” said Hoogenstryd. “Increasing transistor count combined with the modeling of more complex parasitic effects is resulting in transistor-level simulation runtimes doubling and quadrupling. To address this challenge, Synopsys took a unique approach with StarRC Custom by focusing not only on extraction runtime and accuracy, but also on optimizing the extraction data to improve overall transistor-level simulation throughput.”
StarRC Custom is one component in an expanded Synopsys extraction tools suite, which also includes StarRC and StarRC Ultra. Where StarRC Custom is designed for smaller custom digital and analog mixed-signal designs where greater accuracy is required, StarRC is the company’s midrange product, aimed at rapid RC extraction of full chips and very large IP blocks and StarRC Ultra is aimed at high-end designs with a growing list of advanced capabilities.
Ultra provides statistical extraction, which estimates not just mean values but the statistical distributions for parasitic Rs and Cs. It turns out that Synopsys's statistical timing engine has for some time had the ability to use this statistical parasitic data, but most users ignored the capability, focusing instead on active-device parameter statistics. The statistical extraction data can be used to launch Monte Carlo runs for analog simulations. Additional features in the Ultra package will include a link to a CMP simulation tool that will give Ultra extractions a tighter window on interconnect variations due to systematic CMP effects and somewhere down the road will be support for extraction from multi-die structures such as wire-bonded stacked dice or dice connected with through-silicon vias. Ultra is scheduled for general availability also in December.
Figure 3. The Expanded StarRC Extraction Suite