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For this discussion we will differentiate Multi-chip modules (MCM) as essentially dozens of chips interconnected on a small form factor single layer substrate, System-in-Package (SiP) being the 3D chip stacking of bare or packaged chips on a multi-layer substrate and the System-on-Package (SoP) as similar to the SiP with the addition of thin-film passive components on the package substrate. We talked to Agilent, AWR and Mentor Graphics about System-in-Package (SoP) design with a focus on passive component and IC modeling, design flows, design for yield and manufacturing, new issues for CAD and simulation set-up for “full characterization” of multi-mode multi-band devices. Below are the responses from AWR Crop.
Microwave Journal: Multilayer organic substrates use an inexpensive substrate such as FR4 and a low-cost advanced epoxy and polyimide as dielectrics. These substrates form the packaging for SoP devices and are thus frequently found in high-volume applications well into the GHz frequency range. What are some of the simulation issues with using these materials and high-density multi-layer substrates, especially with regard to characterizing parasitic behavior (loss, coupling, etc.) and designing for yield?
AWR: To adequately simulate some of these structures, it is important to go beyond simulation itself and look at the entire design. The SoP structures are most often layout-driven, so to adequately simulate them, you need a seamless flow from layout to simulation. This is true whether the parasitic, or even primary behavior is being modeled using schematic-based models, AWR’s ACE circuit-extracted layout, or shape-based EM analysis using any EM solver technology in the AWR EM Socket.
Some of the dominant aspects of these parasitic effects also span several design domains. This can be as simple co-simulating a circuit-level IC or packaging-level filter design with the “bits” in the overall digital communication system, or much more subtle, capturing IC-to-IC coupling with non-ideal ground planes, bondwires, and module “bumps”. AWR’s UDM and multi-technology design capability allow the engineering team to simultaneously load multiple technologies not only for simulation, but also for complete layout descriptions, verification, and EM analysis. In addition to exploring the design space across the various technology domains, the UDM allows the user to simultaneously explore the design domains by simulating from layout-driven, as well as schematic-driven perspectives.
Finally, for any “DFx” capability, whether it’s Design For Yield, Design For Manufacturing, etc., the essential feature is to have some sort of parametric representation defining the design. Consequently, we need to look more broadly when we talk about simulation, rather than just simulation itself.
Microwave Journal: With so many buried and embedded components, what seems to be the most practical ways for an engineering team to achieve successful integration of multiple die, passive on-board components and interconnects into one module? For instance, is it a piecemeal approach or multiple prototypes or greater reliance on full module verification via EM simulation?
AWR: You have to partition the circuit into workable subcircuits that lend themselves to a top-down, parametric design capability as far into the product development cycle as possible. Once the initial topological selection is performed for complex circuits like MCM or SoP, the designer often switches to an analytical, bottom-up design style based more on EM solvers than on parametric circuit simulation. The design team can forego concurrently designing the coupled subcircuits if the partitioned subcircuits can be designed independently. That is, it can be performed by representing their coupling to other subcircuits or parasitic design elements as definable parametric elements (non-ideal harmonic loads or lumped/distributed models, respectively.
The entire design ultimately must be verified electrically via EM simulation and for manufacturing via DRC, LVS, and DFM. If the team has thoroughly explored the design before verification to understand couplings and sensitivities, it may not be necessary to place the entire design into an EM solver for verification. Instead, the SoP or MCM design can be electrically verified by selective EM analysis. However, it is essential to conduct parametric exploration of the circuit throughout the design process to gain an understanding of the critical dependencies, sensitivities, and couplings.
Microwave Journal: Is the EDA associated with SiP design evolving in a way similar to IC or SoC design with regards to design kits, LVS and DRC?
AWR: It is evolving this way in the sense that each IC and packaging technology has a PDK or design kit with LVS, DRC, and support for AWR routing and interconnect technologies such as bridge codeautomatic via insertion and iNet automated routing. The same demands are being placed on laminate and IC kit development, and perhaps even more as these technologies can be concurrently co-designed, co-simulated, and co-verified within the AWR UDM. However, it is not evolving this way in the sense that the integrating technology is PCB-based and not IC-based. We see a tremendous demand for simultaneously running real-time PCB DRC and using PCB DFM while still verifying RF and microwave electrical performance at the circuit or system level. The AWR Connected for Mentor Graphics Expedition flow supports this type of real-time integration so that as the team works to get the design out the door, the PCB aspects are being altered in the DRC context while the electrical characteristics are simultaneously verified to ensure that performance has not been sacrificed. This is all performed at the parametric, circuit, or system level without reducing the design to “dumb metal” and just subjecting everything to EM simulation.
Microwave Journal: How is multi-layer passive component design and embedded ICs changing the requirements for CAD automation? Can you offer an example?
AWR: Engineers really don’t want to abandon parametric, top-down design because they have a great deal of comfort with the approach as no one actually wants to repeatedly move lines and/or resize components and then run EM simulation for half a day. With this in mind, AWR has developed new technologies specifically designed to solve this problem. For example, EXTRACT is an automated, schematic-driven EM capability that lets users use the schematic- or layout-driven parametric approach to design, but does not require them to manually run the EM solver and then stitch back the resulting, high pin-count S-parameter block into the schematic. ACE can be used in this flow, especially for interconnects, and it delivers results up to 30,000 times faster than EM with comparable accuracy. The same structure can then also or a later time be sent to any EM solver in the EM Socket, including AXIEM, which provides industry-leading speed and accuracy for a general, 3D planar EM solution.
Microwave Journal: CAD data and simulation data (structure geometries for EM) are not necessarily compatible. What is the state of the art in sharing information between the CAD group and electrical design group from the perspective of sharing information between environments?
AWR: We’re excited about this because IFF-based data translation is truly painful. On the IC front, OpenAccess is becoming increasingly popular, and brings platform independence to the IC portion of the design. This allows much more transparency between simulation and verification. For PCB, we’ve just released AWR Connected for Mentor Graphics Expedition that makes PCB-RF co-design truly integrated at the database level for the first time.
Before this, the flows were not well integrated, mainly because the IFF required duplication of all physical and electrical library information from the PCB tool to the RF tool. Even after performing this Herculean effort, the best you could hope for after getting your RF design into the PCB layout was to send everything back for EM because link to circuit simulation was broken. AWR Connected for Mentor Graphics Expedition solves both problems. Libraries are auto-generated in our Microwave Office software from the Mentor library, and circuit simulation is always available from the Mentor layout and schematic. Even the automated, schematic-driven EXTRACT capability can be run in Microwave Office software from the Mentor environment. This flow is so highly integrated that DRC/DFM issues can be “designed-out” in Mentor while simultaneously running a Microwave Office simulation to ensure that electrical performance is maintained. Our recent success story at Alcatel-Lucent highlights all of these points.
Microwave Journal: To reduce the module size, passive elements are buried vertically in the organic laminate package substrate allowing a more efficient integration of the passive elements in an RF front end. Is it more challenging to achieve high-Q passive components with multi-layer organics versus surface mount parts or passive on-chip?
AWR: You can certainly achieve higher Q circuits with integrated passives than with surface-mount parts, but the question is whether you can design them predictably without turning amplifiers into oscillators or dividers, for example (laughter). You need to look at the design from a more holistic perspective within the context of a predictable design methodology. Some design teams won’t go near the integrated passives because they’re not confident their methodology can repeatedly produce a successful design. That is, the risk out-weighs the performance and cost benefits. Other teams have developed methodologies with which they can continue to do predictable, parametric design and are able to leverage vertically-integrated passive structures.
Microwave Journal: For the sake of simulation speed, is it better to use scalable broadband equivalent circuit models for high-Q passive components or do they sacrifice too much accuracy?
AWR: It really depends on where you are in the design flow. Early on, you can start with equivalent circuit models for topology evaluation or even do a first-cut design. As the design flow progresses, you certainly want to get more and more accurate representations, and the point at which you switch from modeling your high-Q passive one way to modeling it another way will depend on what other factors you are evaluating in the design flow. They can include speed, parametric tuning and optimization, and layout-based modeling.
Microwave Journal: Are there decent fully parameterized electrical models for certain “standard” passive components?
AWR: The best models we’ve seen are from Modelithics. They let you scale over package type (0603, 0402, etc.), vary the substrate properties, and still capture the package resonances.
Microwave Journal: Is neural modeling still being investigated by the simulation community?
AWR: AWR continues to pursue several innovative modeling approaches. We’re constantly advancing the ANN neural net model in our APLAC simulation technology in order to expand the number of independent parameters. X-models have also been expanded and proven valuable to the simulation community because they tune and optimize like closed-form models, have the accuracy of EM analysis, and don’t suffer from many of the shortcomings of models based on interpolated S-parameter or MDIF files. Another advanced modeling technique we are actively pursuing is EM-embedded models with which we optimize the 3D EM solver and put it directly in a model, for bond wires or visa, among other things.
Microwave Journal: What level of MMIC and RFIC model detail is necessary and available (in the case of vendor supplied die) for designers simulating a multi-chip module?
AWR: There is insufficient data being supplied at this level. Many MMIC and RFIC customers have to do their own application-specific testing and then use the results at the SoP or system level. The problem is very complex because the loads presented to some of these ICs are not normally characterized by IC vendors. Compounding this, because of the small form factor of the SoP or MCM, is die-to-die coupling. Once you have couplings that cannot be represented at the boundary of a die, you need a circuit-level description of the die to get at some of these problems. A behavioral or compact model of the die is no longer adequate.
Microwave Journal: How many die might be on one of the more complex commercial or military multi-band MCMs today?
AWR: We’ve seen as many as 15 die in an earlier generation system, and the goal was to reduce it to 8 or even 4 die.
Microwave Journal: Is SiP design significantly different than MCM or SoP design from a tools perspective?
AWR: There are people trying to do SiP design totally within an IC flow, and other trying to decouple the electrical circuit simulation from the physical circuit realization for MCM and SoP. This works in both cases if the multiple design domains and technologies don’t significantly couple to each other, which occurs more frequently as you push technology or system requirements. If you have die coupling to packaging or severe layout dependencies driving system performance, you really need a tool that can simultaneously load both the IC and package and then handle schematic, layout, simulation, and verification aspects independently or together. The AWR UDM can be an IC tool, a packaging tool, a PCB tool, or all three by loading simultaneous PDKs for all the manufacturing technologies and allowing for their complete co-design across simulation, layout, and verification.
Microwave Journal: How are designers implementing simulation test benches for all the operating conditions and required metrics that are specified for multiband multimode handsets?
AWR: Designers are using pre-configured simulation test benches for LTE, WCDMA, GSM/EDGE or combinations thereof to perform conformance tests such as ACPR and EVM. The same wireless signal used in simulation may be directly passed on to test equipment to validate and predict the performance of a device.