For this discussion we will differentiate Multi-chip modules (MCM) as essentially dozens of chips interconnected on a small form factor single layer substrate, System-in-Package (SiP) being the 3D chip stacking of bare or packaged chips on a multi-layer substrate and the System-on-Package (SoP) as similar to the SiP with the addition of thin-film passive components on the package substrate. We talked to Agilent, AWR and Mentor Graphics about System-in-Package (SoP) design with a focus on passive component and IC modeling, design flows, design for yield and manufacturing, new issues for CAD and simulation set-up for “full characterization” of multi-mode multi-band devices. Below are the responses from Mentor Graphics.

Microwave Journal: Multilayer organic substrates use an inexpensive substrate such as FR4 and a low-cost advanced epoxy and polyimide as dielectrics. These substrates form the packaging for SoP devices and are thus frequently found in high-volume applications well into the GHz frequency range. The key to properly simulating such substrates - especially for digital signals - is an accurate, wideband dielectric model. Such a model must capture detailed frequency-dependent behavior from DC to many tens of GHz. From an accuracy perspective, frequency-independent or other simplistic approximations are problematic across the wide range of frequencies found in today’s digital signaling; a better fit to realistic behavior is required.

Mentor Graphics: Mentor's signal- and power-integrity tools use a "wideband Debye" model, which correctly predicts a causally declining "dielectric constant" and linearly increasing loss across frequency. For signal-integrity analysis especially, this behavior must be translated to the time domain, where Mentor favors the use of rational polynomial approximation (complex-pole fitting) rather than direct convolution; this approach ensures causality, high performance and accuracy, and perfect correspondence between the time and frequency domains.

Yield is affected by the quite-loose tolerances of materials like FR-4. Such effects can be studied by "sweeping" through time-domain simulations with varying material properties.

Microwave Journal: With so many buried and embedded components, what seems to be the most practical ways for an engineering team to achieve successful integration of multiple die, passive on-board components and interconnects into one module? For instance, is it a piecemeal approach or multiple prototypes or greater reliance on full module verification via EM simulation?

Mentor Graphics: Few companies can afford the time it takes to create prototypes. It really has to work first time. The key to this is co-design and simulation in combination with design tools that really understand the technology you are designing with to provide a “correct by design” flow as opposed to just a drawing board where you add features.

For example, our embedded passive technology manages the entire design flow from material parameters, Manufacturing process related parameters to automatic synthesis of passive thin and thick film components and real time DRC of these to ensure first turn success. In this flow, simulation and analysis are vital components. Initially as early planning tools, but as the design is getting closer to completion, a gradual transition from first-level simulation to full electro-magnetic analysis. Shortcuts in this process are known to cause re-spins and current simulation integrations allow very fast and seamless data transfer between design and simulation to make it practical to run simulations whenever needed.

Microwave Journal: Is the EDA associated with SiP design evolving in a way similar to IC or SoC design with regards to design kits, LVS and DRC?

Mentor Graphics: This is a classic question. Still, the challenges in SiP design are unique and do not lend themselves to borrow methodology from other technology. Clear however, is of course that design kits, which really are just protected templates of proven technology, are being used both to save time and to mitigate the risk of errors. In terms of LVS and DRC, the keyword in SiP design is “real time DRC” and this is true even for 3D related physical and manufacturing rules. Its simply too late to find errors using batch LVS and batch DRC processes even though the batch checks are used as a final sign off process.

Microwave Journal: How is multi-layer passive component design and embedded ICs changing the requirements for CAD automation? Can you offer an example?

Mentor Graphics: This impacts the entire EDA chain. Multi-layer embedded passives are specific technology that requires specific EDA support to be viable. When embedding ICs, you need an EDA flow that can place parts on inner layers and manage unique sets of manufacturing documents for each placement layer. In addition, you need to have parts automatically drop into cavities without having to build special versions of the library. It also offers challenges to the 3D wire bond and parts DRC. As mentioned, DRC has to be real time and with parts on inner layers, it becomes so much more critical that the tool directs you to follow the design rules

Microwave Journal: CAD data and simulation data (structure geometries for EM) are not necessarily compatible. What is the state of the art in sharing information between the CAD group and electrical design group from the perspective of sharing information between environments?

Mentor Graphics: This used to be the case and it was in fact one of the single most costly issues in multi-technology design.

Today we have enhanced our design tools to be able to share the data model of the simulation environments so data can be sent back and forth multiple times without loosing design intent.

This is critical for 2 reasons:
1: You need to simulate frequently and its not acceptable that it takes days or even hours to set up the simulation
2: When issues are found in the simulation, you may want to use the simulator and the simulation environment to correct the issue and write back the changes to the design environment. This requires an exceptionally tight integration like the ones we have with Agilent ADS and AWR Microwave Office for RF design, or our own Hyperlynx environment. To conclude: In the past there were enough difference between the CAD tools and the analysis tools to make data sharing, and thereby run simulation, extremely cumbersome, but that is no longer the case.

We see examples where CAD data are sent to an RF design and simulation tool followed by simulation and optimization and data posted back to update CAD data — all in less than 5 minutes without any manual fix ups.

Microwave Journal: How many die might be on one of the more complex commercial or military multi-band MCMs today?

Mentor Graphics: Interestingly, the typical SiP has a very low die count.-maybe 2-5 dies. Now and then we do come across MCM’s with over 100 dies. However, I have seen this 10+ years ago and it does not seem to have changed much since. To be honest, MCM’s with more than 10 dies are very rare.

Microwave Journal: Is SiP design significantly different than MCM or SoP design from a tools perspective?

Mentor Graphics: We have not really understood why there is a need to differ between MCM, SiP and SoP. Our customers did Stacked die MCM’s with thin film passives many, many years ago before anyone even dreamed up the acronym SoP. Companies use the technology necessary to get the job done and this means that sometimes an MCM suffices while the next design would qualify as an SoP. Clearly if you are not using embedded thin film passives in the substrate, then those particular features are not needed but in most cases, this varies from design to design within the same company so today we rather talk about “Advanced Packaging Tools” having all the capabilities needed to meet the varied design challenges our customers are facing today.