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Industry News / Software & CAD

Agilent EEsof EDA & RF SoP Co-design

February 2, 2009
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For this discussion we will differentiate Multi-chip modules (MCM) as essentially dozens of chips interconnected on a small form factor single layer substrate, System-in-Package (SiP) being the 3D chip stacking of bare or packaged chips on a multi-layer substrate and the System-on-Package (SoP) as similar to the SiP with the addition of thin-film passive components on the package substrate. We talked to Agilent, AWR and Mentor Graphics about System-in-Package (SoP) design with a focus on passive component and IC modeling, design flows, design for yield and manufacturing, new issues for CAD and simulation set-up for “full characterization” of multi-mode multi-band devices. Below are the responses from Agilent.

Microwave Journal: Multilayer organic substrates use an inexpensive substrate such as FR4 and a low-cost advanced epoxy and polyimide as dielectrics. These substrates form the packaging for SoP devices and are thus frequently found in high-volume applications well into the GHz frequency range. What are some of the simulation issues with using these materials and high-density multi-layer substrates, especially with regard to characterizing parasitic behavior (loss, coupling, etc.) and designing for yield?

Agilent:The frequency domain linear simulation technology that produces S-parameters was the primary simulation technology for conventional RF/MW circuit designs. The analytical circuit models such as microstrip, stripline, and co-planar are extensively used in the simulations, however it assumes the physical structure to be simulated must be as close as the structure modeled, for example ground planes and enough spacing to other adjacent traces. Due to the smaller form factor for high volume applications, it is practically impossible to avoid the parasitic behavior of multilayer designs. The two most important simulation issues in the multilayer designs are the inclusion of imperfect grounding effect and coupling due to the proximity between parts to parts and traces to traces or even for traces to the ground planes. All of these can be addressed by brute force complete EM simulations. Nevertheless the ultimate design challenge from multilayer circuit designers’ standpoint will come from how to pin-point the source of problem area. The reason is because the traditional EM simulation only provides final results on whether the structure is working or not (black box S-parameters). A more elegant technique called Coupling Analysis, pioneered by Agilent EEsof EDA, enables different combinations of suspect coupling structures to be simulated by including or excluding certain objects and setting up different coupling distances, and the resultant S-parameters and visualization of current field plots provide a way to identify the impact of parasitic behavior (loss, coupling, radiation, etc) AND where it is occurring so that the designer can fix it.

The design for yield has also been an important design or simulation challenge for multilayer SiP designers. It is because of the requirement of extensive simulation power for statistical EM simulations. However this can be addressed by adopting statistical design techniques of: a) Sensitivity analysis to understand and identify design parameters by their impact on performance specs; b) Design of Experiments (DOE) simulation to further pareto the parameters and interactions amongst parameters that impacts performance while they are allowed to vary across their tolerance ranges in all possible combinations. The most sensitive components identified demand the engineer to pay particular attention to their layout, grounding, shielding and coupling analysis to design for yield. See

Microwave Journal: With so many buried and embedded components, what seems to be the most practical ways for an engineering team to achieve successful integration of multiple die, passive on-board components and interconnects into one module? For instance, is it a piecemeal approach or multiple prototypes or greater reliance on full module verification via EM simulation?

Agilent:The nature of components used in SiPs is a complicated combination of different technologies. As an example, the active dies require time or frequency domain simulations depending on the content of design whereas buried and embedded passives typically require EM simulations. The challenge of achieving a successful integration of multiple dies, passives, and interconnects into one module eventually becomes the co-design of different technologies, which demands a very solid high frequency and high speed co-design platform. The ultimate solution for passives and interconnects is the full module verification via EM simulation, however this is only makes sense for final design verification due to the extremely time consuming simulation processes. A more practical approach for an engineering team is a piecemeal approach but bring all of them into co-design platform for analyzing and optimizing the dynamic interactions between them. To speed up the passive circuit design process for the piecemeal approach, the technique that builds parameterized scalable EM models for passive structures based on accurate EM simulation using the patented technology called Multi-dimensional Adaptive Parameter Sampling (MAPS) technology of AMC (Advanced Model Composer) can be also used. See

For the integration of active dies into the full module simulations, the most difficult problem is to ensure the best accurate models for the die. Unless the active dies such as amplifiers or mixers are designed in-house, it is difficult to obtain accurate non-linear models of these components to do a full module simulation. A possible way is the use of behavior models. Now it is easy to include them for the full module simulations with the latest invention of non-linear X-parameter models from Agilent Technologies. X-parameters can be generated from simulation with ADS or measurement with the non-linear vector network analyzer (NVNA) . X-parameter models capture the non-linear characteristics of amplifiers, mixers or transistors including frequency mixing and cascaded impedance mismatches.

Microwave Journal: Is the EDA associated with SiP design evolving in a way similar to IC or SoC design with regards to design kits, LVS and DRC?

Agilent:Not necessarily. As we discussed in the previous questions, the more challenges exist in multiple technologies used in SiP than IC or SoC designs. Therefore the EDA technology is evolving more to the co-design concept which can be divided into front-end co-design for simulation perspective and back-end co-design for layout/assembly/packaging perspective. For the front-end co-design, the trend is in the integration of different simulation domains into a single unified design platform which can be called high frequency and high speed co-design platform. For the back-end co-design, the trend is in the integration of different back-end tools which has different technology files and design/assembly rules.

Microwave Journal: How is multi-layer passive component design and embedded ICs changing the requirements for CAD automation? Can you offer an example?

Agilent:For the physical implementation, the CAD requirements are: a) unified stackup; b) connectivity support; c) electrical rule check (ERC); d) design rule check (DRC); and e) assembly rule check across chip, module and board.

For simulation, an example is moving large spiral inductors off an RF chip to become an embedded multi-layer component to reduce the cost of semiconductor area used. The impact on CAD automation means that it now has to support co-design of the chip and module with simulation to accurately account for the 3D interconnects such as wire bonds or solder-bumps along with the embedded active system or circuit ICs. Co-design requirements necessitate the tight integration of system, circuit and 3DEM simulators under the same co-design platform. Standalone 3DEM tools cannot support this kind of flow.

Microwave Journal: CAD data and simulation data (structure geometries for EM) are not necessarily compatible. What is the state of the art in sharing information between the CAD group and electrical design group from the perspective of sharing information between environments?

Agilent:Yes, it is true that CAD data and structure geometry data for EM are not necessarily compatible. One example is via holes. Via hole in CAD data format is true representation of physical structure, for example very small arc resolution for circles. However the required via holes in EM simulation don’t have to be that complex since it creates more simulation burden without improving the accuracy of simulation. The state of art for design flow integration is intelligence of CAD data translation process. As demonstrated in Agilent EEsof EDA design tools, the via holes from the CAD environment can be simplified into rectangular or polygonal vias for faster EM simulations without manual CAD manipulation. Also it is important to automatically import substrate stackup imformation without manual intervention.

Microwave Journal: To reduce the module size, passive elements are buried vertically in the organic laminate package substrate allowing a more efficient integration of the passive elements in an RF front end. Is it more challenging to achieve high-Q passive components with multi-layer organics versus surface mount parts or passive on-chip?

Agilent:It is a design trade-off between performance, size, and cost. Surface mount parts typically have the best Q factor whereas integrated passives have the size advantage with less parasitic behaviors. It is more challenging in nature since the materials used in the organic laminate substrate comes with higher losses.

Microwave Journal: For the sake of simulation speed, is it better to use scalable broadband equivalent circuit models for high-Q passive components or do they sacrifice too much accuracy?

Agilent:A better way to keep the fast simulation/optimization speed without losing the accuracy of models is to develop an EM based scalable passive model library that can be used in other circuit or system simulations. (see the answer to Q2 above) Typical issues with the broadband equivalent circuit models are 1) difficulty to develop a good model that fits to wide frequency range 2) scalability of models for different sizes.

Microwave Journal: Are there decent fully parameterized electrical models for certain “standard” passive components?

Agilent:Yes. AMC was developed to overcome the difficulty of creating accurate fully parameterized scalable electrical models of standard passive components such as spiral inductors, transitions, interconnects, and arbitrary geometries, with the patented Multi-dimensional Adaptive Parameter Sampling (MAPS) technology that allows modelers to build parameterized scalable EM models. The AMC models run at the speed of circuit models but with the EM level accuracy.

Microwave Journal: Is neural modeling still being investigated by the simulation community?

Agilent:Neural network is actively being researched for use in modeling time-dependent non-linear behavior where no good empirical or analytical models exist. One application is modeling the memory effects of power amplifiers.

Microwave Journal: What level of MMIC and RFIC model detail is necessary and available (in the case of vendor supplied die) for designers simulating a multi-chip module?

Agilent:The most accurate model available with full IP protection is X-parameter model and can be generated by measurement with Agilent NVNA or simulation with ADS. X-parameter is the mathematically rigorous extension of S-parameters to fully capture non-linear behavior that includes frequency conversion and impedance mismatched harmonics of cascaded non-linear components. When measured or simulated with load pull termination, the X-parameter models are valid across a wide range of terminating impedances. Today, measurement based X-parameter models are limited to 2 ports due to available hardware instrumentation, but simulation based X-parameters can be generated for multi-port non-linear components such as mixers and transceiver. Early beta customers represent IC design houses and major handset vendors are fully embracing X-parameter model because it provides a compact accurate language to communicate and simulate non linear behavior of MMIC, RFIC, PAM and FEM between design partners.

Microwave Journal: How many die might be on one of the more complex commercial or military multi-band MCMs today?

Agilent:Here is a picture of a multi-band MCM in a TOPs package used in a pulse compression radar. There are 7 MMIC dies in this one MCM. The full writeup of this design is attached here.

Microwave Journal: Is SiP design significantly different than MCM or SoP design from a tools perspective?

Agilent: Yes and No. SiP designs are quite different from MCM due to the use of embedded passives in the substrate. However from the packaging and use of multiple dies, they are quite similar designs. Since SiP and SoP can be interchangeably used in some aspects, there isn’t much differences between the two.

Microwave Journal: How are designers implementing simulation test benches for all the operating conditions and required metrics that are specified for multiband multimode handsets?

Agilent: This is a very difficult task for designers because they not only have to design, but also have to understand the thick documentation related to all the latest multi-mode standards such as 3GPP-LTE and WiMax along with older 2G standards such as GSM or CDMA. Then they have to translate this to set up the spec-compliant source modulation, power levels, bias variations, measurement of EVM, ACPR and BER in the simulation test benches. It is almost impossible to do without the help of preconfigured spec compliant test bench libraries. Fortunately, Agilent provides first-to-market availability of these libraries for the latest 3G and 4G wireless standards. See These libraries share the same signal generation and processing algorithms that goes into the Agilent signal sources and analyzers. This means that design verification with these ADS wireless test benches are fully consistent with actual hardware measurement procedures so that any deviation from specs can be confidently attributed to the design and not to the simulation algorithms or test bench set up mistakes.

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