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Integer-N PLL Local Oscillator for Satellite Telecommand Receiver

December 2, 2008
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This article describes the design and implementation of L-band frequency synthesizer based Local Oscillator to down-convert the uplink signal in a Telecommand Satellite Digital Receiver. An Integer-N PLL scheme was implemented to achieve a compact and low power module. The Local Oscillator when tested with the Receiver successfully achieved all performance parameters for satisfactory operation of the total system.

Fundamentals
There has been an ever-increasing demand for low cost, low power, miniaturized frequency sources that can be conveniently configured to generate any predefined frequency without major changes in the circuit and without elaborate testing. A frequency synthesizer is a system that can generate several distinct frequency signals from a single reference source or time base.


In a satellite system, a synthesizer finds applications as a transmitter carrier; as a local oscillator for up/down conversion; or as a frequency multiplier. Important features of a frequency synthesizer are frequency stability (ppm/°C), phase noise (dBc/Hz), frequency resolution (Hz), signal power (dBm), switching time (sec), spectral purity (dBc), power consumption (W), size and cost. In a satellite system size, weight and power play a dominant role in the choice of any particular architecture.

Techniques used for frequency generation include conventional methods using frequency multipliers, Direct Digital Synthesizers DDS, Integer-N PLL, Fractional-N PLL, Sample Phase Lock Detector SPLD. The choice of a technique for any given application is governed by the factors given above.

For example if sub-hertz resolution is desired then DDS based architecture is the ideal choice. Our requirement was to generate two 7dBm signal sources at 1888.8 MHz and 188.88 MHz with ± 2 ppm frequency stability over a temperature of -10°C to +50°C. The Local Oscillator was also subjected to vibration and thermovac tests before qualifying it for flight. We required a phase noise of –95 dBc/Hz at 1 kHz offset and a spectral purity of better than –40dBc. Integer-N PLL architecture was chosen for deriving these signals in a compact and low power fashion.


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Recent Articles by Muddaser Mohiyuddin, Rathna Kumar M, Jacob Mathew, Puneet Kumar Pandey, ISRO Satellite Centre

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