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Mentor Graphics Boosts Eldo Simulator Performance

November 6, 2008
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Mentor Graphics Corp. announced a new version of the Eldo® transistor-level analog simulator that offers improved raw speed performance without compromising accuracy. The speed up targets very large post-layout simulations that are mandatory at 45 nm processes and below to thoroughly verify a complex design.

Final verification simulations routinely include hundreds of thousands of devices and millions of coupled parasitic devices originating from complex layout extraction. Two key synergetic improvements to the Eldo simulator have been developed to address the new paradigm of matrices with millions of coupling elements. First, an entirely revised matrix solving strategy provides dramatic speed up over the previous version. Second, new and highly scalable multi-threading technology allows users to take advantage of inexpensive multi-CPU hardware.

Using four CPUs, the observed speed up ranged between 3 to 10x depending on the circuit ‘signature’ in terms of the ratio of active devices to parasitic elements. The new architecture was validated on thousands of circuits ranging from ‘small’ phase-locked-loops or converters to much larger power management circuits or DRAM circuits. On average, larger circuits experienced a greater speed up. The speed up also opens the door for circuits that were simply too large to simulate with genuine SPICE level accuracy. Now, power nets or clock trees become reasonable targets for this level of simulation.

At the 45 nm node, not only are post-layout simulations mandatory to avoid silicon re-spins, but these simulations have to retain the full details of the carefully extracted interconnect couplings. Many of these parasitic elements appear small, but when hundreds of them are combined, the impact upon performance or even functionality can be devastating.

“When developing this project, compromising simulation accuracy was not an option,” said Jue-Hsien Chern, vice president and general manager, Mentor Graphics. “When IC designers have spent considerable effort obtaining an accurate post-layout netlist, they don’t want a SPICE simulator to ‘simplify’ or ignore the parasitic elements. The task of a reliable analog simulator is not to silently manipulate the input netlist until it can compute some approximate waveforms in a reasonable CPU time. We listened to our customers and developed the right technologies to meet their challenge. Combining advanced math and sophisticated computer science, we developed a dedicated matrix solving technology amenable to efficient, generalized multi-threading. Not a single parasitic coupling capacitance is ignored and not a single digit of precision is lost.”

Designers benefit because the entire simulation process that includes matrix solving and device evaluations is now efficiently multi-threaded, and the speed up scales well with the number of CPUs. Since no tuning of the process is necessary, the improvements translate into a measurable net increase of productivity and/or verification coverage.

The new technology is fully and transparently integrated into the ADVance MS™ (ADMS) tool, Mentor’s single-kernel, language-neutral functional verification environment for digital, analog, mixed-signal and RF circuits. The new release of the simulator is part of the AMS 2008.2 release.


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