- Buyers Guide
5G and IoT Supplement
Analog Devices Inc., a leader in semiconductors for signal processing applications, introduced a pair of clock-generation and distribution ICs with the industry’s best combination of device integration, low noise, low jitter performance and signal output flexibility. The AD9520 and AD9522 multi-output clock generators include a 512-byte embedded EEPROM memory block, affording system engineers a programmable clock solution that can serve as both the source and system clock. By programming their own specific set of output conditions using the on-chip memory, designers can easily configure the AD9520/2 as the source clock to ensure initial processing functions are synchronized when the system is powered on or reset. Competing clock ICs require a separate source clock, which must be independently matched to the system processor or microcontroller in order to program the system clock chip, adding component count, cost and complexity to network line cards, wireless and broadband infrastructure, medical imaging, and data converter clocking designs.
”Outstanding jitter performance was the primary reason TruePosition chose the AD9520 for use in our third-generation wireless location measurement unit,” said Alan Larrabee, vice president of research and development for TruePosition. “The AD9520 has a versatile multiple output architecture, integrated PLL, and on chip EEPROM, which provide an elegant solution for sampling clock generation and distribution.”
In addition to the on-chip EEPROM and PLL, the AD9520/2 integrates dividers, fanout buffers and a VCO that tunes from 1.4 GHz to 2.95 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz also can be used. The PLL/VCO clock-generation circuitry boasts phase noise of -150 dBc/Hz at a 10 kHz offset on a 200 MHz clock signal, while the clock distribution fanout channels feature ultra-low wideband jitter performance of 225 femtoseconds.
Two reference inputs allow glitch-free switchover for applications requiring redundant references, while a PLL holdover mode maintains the output frequency in the event of a lost reference signal. Zero delay operation is available to ensure precise phase alignment between inputs and outputs. The AD9520 offers 12 differential low-voltage positive emitter-coupled logic (LVPECL) outputs in four groups, each with a 1 to 32 divider and phase delay. The AD9522 includes 12 differential low-voltage differential signaling (LVDS) outputs. Both devices alternatively offer up to 24 single-ended CMOS output configurations up to 250 MHz.
The AD9520 is available now in production quantities. The AD9522 is available for sampling and will be released in October. The AD9520 and AD9522 come in a 64-lead lead-frame chip-scale package (LFCSP) and are priced at $12.65 per unit in 1,000-unit quantities.
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