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The landscape for analog custom IC EDA seems to be changing with the announcement this week from Synopsys that they are entering the custom analog IC design space with the introduction of Galaxy Custom Designer™ . In a move seeming to go head-to-head with the current dominant tool in this space (Cadence Virtuoso), Galaxy Custom Designer delivers a familiar user interface while integrating a common use model for simulation, analysis, parasitic extraction and physical verification.
It is the first-ever implementation solution built natively on the OpenAccess database for legacy designs as well as a new componentized infrastructure offering unprecedented openness and interoperability with process design kits (PDKs) from leading foundries.
In his keynote speech at the Synopsys User Group (SNUG) in Newton, MA, Aart de Geus, chairman and CEO of Synopsys stated “Our customers have long requested a modern alternative to the custom design solutions currently on the market, by starting with a state-of-the-art, open architecture and tightly coupling it to the Galaxy Design Platform as well as our analog/mixed-signal verification and IP solutions, Synopsys aims to do for custom design what we have done for digital implementation.”
Galaxy Custom Designer with its native open architecture promises to support interoperable PDKs, an integral part of our Open Innovation Platform™, helping designers innovate in analog and full-custom design, according to Fu-Chieh Hsu, Vice president of Design & Technology Platform at TSMC.
TSMC is apparently collaborating with Synopsys to develop the industry’s first interoperable PDK in 65 nanometer, a single PDK that supports multiple environments, including the latest innovations such as Custom Designer. The foundry was represented at the User Group gathering by Tom Quan, Deputy Director, EDA & Design Service Marketing Program who vowed that TSMC would continue to work with Synopsys and the Interoperable PDK Library (IPL) Alliance to accelerate the deployment and adoption of interoperable PDK across the industry.
The goal would be to reduce the need to develop and support multiple proprietary PDKs from multiple EDA vendors. Instead, focus could be spent on developing a single PDK that was interoperable between tools from different vendors.
The demonstration of the new tool was very impressive and the user interface certainly had a look and feel that should appeal to seasoned RFIC designers use to the Virtuoso environment. Synopsys representatives claimed the similarities between environments would ensure a short learning curve for new users (productivity in 15 minutes). The environment also linked schematic and layout, allowing electrical and physical design to happen concurrently.
Here’s a quick overview of what is presented in the product literature. For more details, download the layout editor and/or schematic editor PDF files below.
Custom Designer LE is state-of-the-art layout entry and editing, enabling users to meet the challenges of today’s nanometer designs, editing tasks are accomplished with fewer clicks, quicker menu access, and less pop-up menu clutter. Architected from the ground up, Custom Designer LE enables ultra-fast layout editing with advanced P-cell support and time-saving layout automation through capabilities like intelligent multipart paths that maintain DRC correctness. An integral component of the full Custom Designer system, the tool provides transistor-level layout and editing capabilities in a unified platform for both cell-based and mixed-signal custom content which speeds complex chip design and integration tasks.
Key Benefits include: One unified platform for both cell-based and custom content to speed complex chip design and integration tasks; support for Synopsys ’ Hercules ™ DRC/LVS nd Star-RCXT ™ ; flows for industry sign-off physical verification; support for the IPL Alliance ’s Interoperable PDK libraries for industry-wide design data sharing; and provides multiple layer purpose pair browsers in a single session when editing designs in multiple libraries.
SE ’s real-time connectivity with dynamic net highlighting continuously maintains up-to-date design integrity to speed design and reduce effort and errors related to design entry. An integral component of the full Custom Designer system, schematic editing and analysis capabilities are unified into one platform for both cell-based and custom content, speeding complex chip design and integration tasks.
SE allows access to Synopsys’ leading AMS simulators including HSPICE, HSIM XA, NanaSim XA and WaveView Analyzer. During simulation and debug, the tool provides quick access to any simulator through simple pull-down menus.
Sample of Schematic editor features include:
The schematic editor provides dynamic net highlighting, which instantly shows the user all wires in the circuit with the same net names helping designers avoid the most obvious mistakes. On-canvas editing allows designers to quickly change parameter values, pin labels, net and instances names directly by simply pointing at the object and hitting the return key. SE also automatically triggers library callbacks when editing parameter values thus eliminating tapeout-killing design synchronization problems.
Custom Designer Layout Editor Data Sheet PDF
PDF 1.8 Mb
Custom Designer Schematic Editor Data Sheet PDF
PDF 1.8 Mb
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