Cadence Design Systems Inc., a leader in global electronic-design innovation, announced that Integrated Device Technology Inc. (IDT), a leading provider of mixed signal semiconductor solutions that enable the digital media experience, was able to quickly deliver an IDT PanelPort™ device, an innovative DisplayPort-compatible digital display receiver and timing controller device, in part due to the novel use of Cadence® Conformal® Constraint Designer as a SDC constraint signoff tool. By using Encounter Conformal Constraint Designer for sign-off, IDT was able to improve the quality of the design, avoid costly design iterations and accelerate time to market for this key product.

Frequently, semiconductor designers forgo the additional step of signing off design constraints, but in doing so, they risk creating an error that could jeopardize the final chip. Encounter Conformal Constraint Designer automates the generation, validation and refinement of timing constraints used in semiconductor design. By using the Encounter Conformal Constraint Designer technology as a constraint signoff tool, IDT was able to detect, analyze and correct the constraints early in the design phase.

"Cadence offered to show us how to use Conformal Constraint Designer as a sign-off tool," said Ji Park, vice president and general manager of Digital Display Operation of IDT. "Right away, the tool identified a significant issue that would likely have caused a respin. By using Conformal Constraint Designer in this manner, it is clear that the software can easily pay for itself in added value."

"IDT is an example of a company that realized significant benefits by approaching constraint signoff in a fundamentally different way, using Cadence Conformal Constraint Designer," said Yoon Kim, marketing director for the Cadence IC Digital group. "We have every confidence that a wide variety of designs can benefit from this approach, saving design time, cost and time to market."