Jacket Micro Devices Inc. (JMD) announced that laminate-based radio frequency system-in-package (RF SiP) products made with its patented Multi-Layer Organic (MLO) process have passed JEDEC reliability qualification testing. The MLO substrates, and modules assembled using them, are lead (Pb) free and RoHS-compliant.
WLAN front-end modules using HDI 6-layer MLO substrates and containing both GaAs and SiGe die, assembled with standard wire-bond assembly techniques, were subjected to JEDEC test methods common to the semiconductor industry. Under an LTPD 5 percent sampling plan (0 rejects allowed per 45 samples, per lot) there was no performance degradation or failures.
Manufacturing test specifications were used as the pass/fail criteria for initial and final RF tests, as well as CSAM for evaluating delamination during exposure to moisture soak and solder reflow. Modules passed pre-conditioning to MSL-3 at 260°C per JEDEC J-STD-020C, unbiased HAST (JESD22-A118), 500 hours HTOL (JESD22-A108C), 500 temperature cycles (JESD22-A104C), 45 thermal shock cycles (JESD22-A106), and biased HAST (JESD22-A110). The MLO substrates were fabricated at Microcircuit Technology in Singapore.
“We are very pleased with the initial results of our reliability qualification program” said Rick Clancy, JMD’s director of operations. “The key materials selected for MLO have outstanding environmental characteristics, such as low moisture uptake and high transition temperatures, so we were expecting to see results as good as or better than standard laminate packages. Reliability qualification for semiconductor products is a continuous process and we will be conducting additional tests to ensure that SiP products using MLO meet the stringent requirements of the consumer electronics industry.”