Cadence Design Systems Inc., a leader in global electronic-design innovation, announced that Japan's Semiconductor Technology Academic Research Center (STARC) has incorporated the Cadence® Encounter® Timing System as part of its PRIDE V2.0 Reference Design Flow. The inclusion of the Cadence Encounter Timing System in the reference flow is expected to help STARC member companies and their customers achieve the benefits of advanced process nodes with a powerful signoff solution that increases productivity, performance and predictability for advanced consumer, communications and mobile electronic designs. The announcement follows months of rigorous testing by STARC engineers using multiple test designs on multiple process nodes.

"When Cadence asked us to define what we would need to achieve static timing analysis signoff at advanced process nodes, STARC member companies related a wide range of flow and ease-of-adoption requirements," said Nobuyuki Nishiguchi, vice president of the Development Department-1 at STARC. "After extensive evaluation and testing, we found the Cadence Encounter Timing System was ideal for the PRIDE V2.0 Flow based on its accuracy, comprehensiveness and performance. Designers now have an advanced timing signoff analysis that provides consistency through the design flow and accounts for the interdependencies of timing, signal integrity and power."

Successful digital chip design hinges on timing closure -- and timing closure depends on accurate, correlated signoff-quality timing throughout implementation, optimization and analysis. Conventional solutions typically use one or several timing engines for implementation and another for signoff analysis. But at advanced nodes, accurate timing analysis signoff is a multi-dimensional challenge, and a single view of timing is critical. Factors like signal integrity, IR drop and silicon variability affect signal delay and final timing results, which makes consistent and accurate modeling essential for credible signoff timing analysis and design closure.

The Encounter Timing System is a complete and integrated electrical signoff environment, enabling faster optimization, debug, statistical analysis and final verification of designs for timing, signal integrity and power. Its innovative interface provides a common electrical view through every stage of the design flow, enabling significantly increased productivity and accelerated time to market while supporting a robust debug environment that facilitates rapid diagnosis of multi-dimensional and interdependent design-closure issues. The Encounter Timing System is also an integral element of the Cadence SoC Encounter™ RTL-to-GDSII system, where it helps to reconcile timing and improve the overall predictability, productivity and performance of the design process. And because it handles industry-standard formats, any designer using any design flow will benefit from its unprecedented usability and ease of adoption.

"STARC and Cadence worked closely to validate and deliver the PRIDE V2.0 Reference Flow with the Encounter Timing System to our customers," said David Desharnais, group director of IC Digital product marketing at Cadence. "Our collaboration with STARC puts in place another vital link for both front-end logic designers looking for high-quality timing analysis and ease of use, as well as back-end implementation engineers requiring silicon-accurate signoff. It also highlights the growing number of foundries and design houses around the world that rely on the Cadence digital IC design flow."