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A Fully Integrated CMOS VCO for DCS-1800 Direct Conversion Receivers
The goal of this article is to prove that restrictive phase noise requirements can be achieved with a fully integrated CMOS VCO if the LC tank circuit is properly designed. The VCO has been designed in a standard two-metal layer process with 0.8 mm CMO...
The growing demand for mobile communications, mainly telephony, implies the need for better performance of RF transceiver architectures. A fundamental element in these front-ends is a voltage-controlled oscillator (VCO), the performance of which is a determining factor related to system limitations. Fully integrated VCOs usually suffer from poor phase noise characteristics, so a large effort is made to improve the phase noise of integrated oscillators. As the phase noise of LC integrated VCOs highly depends on the quality factor of the tank circuit,1 special emphasis must be made in the design of the inductor and varactor.
The phase noise performance required for mobile telecommunication standards like GSM or DCS-1800 is so restrictive that it is not easily achieved in a low cost standard technology used in a fully integrated oscillator, in large part because of the limited quality factor of the integrated inductors. However, this article will show that the proper design of the tank circuit allows the design to meet the phase noise specification.
The need for good performance suggests that most integrated RF VCOs are realized with bipolar devices, due to their low high frequency noise.2,3 It will be shown that an oscillator can be implemented in a “big” channel length CMOS standard technology without an excessive increase in power consumption. The technology used is a two-metal layer process with 0.8 mm CMOS transistors.
The selected architecture for the VCO with an integrated LC tank circuit is shown in Figure 1. It is important to mention that a differential architecture has been used to minimize effects such as voltage supply, and current source noise and temperature variations.
There are different architectures used to integrate a MOS VCO.4 The CMOS configuration offers the best phase noise/power consumption ratio. Because MOS transistors need high bias currents to obtain good transconductances, this is the configuration selected to implement the oscillator, expecting a reduction in the power consumption for a same phase noise value, compared with other architectures.
Two tail capacitors have been added in parallel with the biasing current source since their presence can improve the phase noise of the oscillator.5 Simulations show that not only is the phase noise improved but the output power is increased with an insignificant reduction of the oscillation frequency. To select the value of these capacitors, there is a trade-off between the improvement in phase noise and output power, and the sensitivity of the oscillator to supply voltage variations5 and the occupied area.
Two external pins called Vc1 and Vc2 can control the current flowing across the core and the output stage of the VCO, respectively. This way the relation between phase noise and power consumption can be optimized.
Tank Circuit Design
As mentioned before, good phase noise values can be reached by a proper design of the tank circuit. Therefore, the analysis and characterization of the passive elements is a critical step in the design flow. The well-known Leeson model1 demonstrates that the phase noise performance is highly dependent on the quality factor of the tank circuit; therefore, it is necessary to design high Q passive elements.
In the frequency range where the designed VCO works (approximately 1.8 GHz) the inductor usually dominates the quality of the tank circuit.1 Consequently, this section will emphasize the design of this inductor.
The two main factors that affect the quality of an inductor are its resistive and substrate losses. At low frequencies, the series resistance of the inductor metal tracks represents the dominant losses. As the frequency increases, however, eddy currents in the tracks and substrate increase these losses. None of these effects is negligible near 1.8 GHz.
The CMOS architecture selected to design the oscillator is differential, so the tank circuit must have a differential behavior as well. The balanced one is the only type of inductor with differential behavior. Another solution is to use two standard inductors symmetrically placed. This option has been rejected due to the larger area occupied. Since the technology uses a highly conductive P type substrate, the substrate losses, and thus the area of the inductor, will determine its quality.
The selected configuration is the balanced one, due to the possibility of integrating the same inductance in less area. Balanced inductors exhibit more coupling between their turns, which means a larger inductance can be obtained than for two standard inductors symmetrically placed occupying the same area. Furthermore, this inductance is obtained with less metal length and the resistance of the inductor decreases.6,7 In addition, the parasitic coupling that occurs between the two inductors symmetrically placed is avoided using a balanced inductor.
Besides substrate losses, resistive losses of the inductor cannot be neglected. In order to reduce the ohmic losses of the metal tracks two improvements have been made: the connection in parallel with longitudinal vias (except in the underpasses) of the two available metal layers to diminish the series DC resistance of the coil and the design of a hollow spiral to avoid the high resistance of the inner turns due to proximity effect.1 A microphotograph of the balanced inductor is shown in Figure 2 and its geometrical characteristics are presented in Table 1.
The measurement system used for the characterization of the passive elements consists of an HP8719ES vector network analyzer and ACP40 GSG microprobes. To calibrate the measurement system, the short open load thru (SOLT) method has been used. Finally, the four step de-embedding method8 has been used to remove the parasitic effects introduced by the measurement structures. The measurement results of the inductor after the de-embedding procedure are presented in Figure 3.
Due to the symmetry of the inductor, S11 and S22 parameters should be exactly equal, as are S12 and S21. As seen, the measurement results of the two ports are very close together. To improve the accuracy of the measurements, after calculating the one port S-parameters using
Their difference must be evaluated. If the calculated difference is higher than five percent the measurements are rejected and must be made again, otherwise, an average one port S-parameter is calculated
With these average one port S-parameters, the inductance and quality factor of the inductor can be calculated. The results are presented in Figure 4.
The final step of the characterization process is the modeling of the inductor. A Π Model has been used due to its simplicity and physical sense.6 Moreover, it is easy to fit the model in a narrow band of frequencies. One of the limitations of the Π model is that it is not valid for modeling passive elements in high frequency ranges. However, because the designed oscillator operates at a fixed frequency, the Π model is accurate enough in the frequency range from 1.7 to 1.9 GHz. The model of the inductor is presented in Figure 5. The series resistance has been divided into two parts only to make explicit that the inductor is balanced.
The varactor design is based on the variable capacitance that appears in a P-N junction when it is reverse biased. The varactor consists of P+ islands diffused in an N-well and surrounded by a N+ zone. This way, the depletion zone appears around all the P+ diffusion, so the capacitance is higher as is the capacitance variation.6
The N-well N+ contacts are useful in decreasing the series resistance of the device. The geometrical characteristics of the varactor are presented in Table 2 and a microphotograph is shown in Figure 6.
The measurement system, calibration and de-embedding methods used to characterize the varactor are the same as the ones used to characterize the inductor. The measured results are shown in Figure 7.
The oscillator response has been measured with a E4407B spectrum analyzer. DCQ-05 PPGPP microprobes have been used for the supply and control voltages, and ACP40 SGS microprobes have been used for the output signal.
A microphotograph of the VCO is shown in Figure 8. In the layout, some capacitors between the DC voltage pads and ground have been added in order to stabilize the supply voltage, eliminating the high frequency variations in this voltage that can adversely affect the phase noise response. The last consideration is that various substrate contacts connected to the ground pads were added around the transistors in order to provide a stable substrate potential.
The measured phase noise response of the VCO at 1.8 GHz is shown in Figure 9. This measurement has been done for a bias current of 8 mA for which the optimum performance of the oscillator is obtained. With this current, the oscillator is operating in the current-limited region but near the limit of the voltage-limited region.5 The rest of the measurements, presented in Table 3, have been done with this same current.
In order to design a VCO which fulfills restrictive phase noise requirements, the first stage is to design a good quality tank circuit, which in this case is based on a balanced inductor and a PN junction varactor. The quality factor of the inductor is 7.7 at 1.8 GHz and the varactor has a quality factor between 30 and 50 depending on the applied control voltage.
A fully integrated VCO with low core power consumption that achieves the restrictive phase noise specification for DCS-1800 has been designed. The measured phase noise is –103.8 dBc/Hz at a 100 kHz offset from a 1.8 GHz carrier. The oscillator has been designed using 0.8 mm CMOS transistors; therefore, the ability of the CMOS technology to achieve good phase noise results, if a proper LC tank is designed, is demonstrated.
1. J. Craninckx and M. Steyaert, Wireless CMOS Frequency Synthesizer Design, Kluwer Academic Publishers, 1998.
2. H.D. Wohlmuth, et al., “2 GHz Meissner VCO in Si-bipolar Technology,” 29th European Microwave Conference Digest, 1999, pp. 190–193.
3. M. Zannoth, et al., “A Single Chip Si-bipolar 1.6 GHz VCO with Integrated-bias Network,” IEEE Transactions on Microwave Theory and Techniques, Vol. 48, No. 2, February 2000, pp. 203–205.
4. J. Hernández, H. Hein, F. Oehler and A. García-Alonso, “Analysis of Architectures for 1.8 GHz CMOS LC-tank Voltage-controlled Oscillators,” XIV Design of Circuits and Integrated Systems Conference, November 16-19, 1999, pp. 137–142.
5. A. Hajimiri and T.H. Lee, The Design of Low Noise Oscillators, Kluwer Academic Publishers, 1999.
6. J. Aguilera, “High Quality Factor Integrated Inductors in a Standard 0.8 mm SiGe Technology,” PhD Dissertation, 2002.
7. A.M. Niknejad, R.G. Meyer and J.L. Tham, “Fully Integrated Low Phase Noise Bipolar Differential VCOs at 2.9 and 4.4 GHz,” Proceedings of the 25th European Solid-State Circuits Conference, 1999, pp. 198–201.
8. T.E. Kolding, “On Wafer Calibration Techniques for Gigahertz CMOS Measurements,” Proceedings of IEEE International Conference on Microelectronic Test Structures (ICMTS), March 1999, pp. 105–110.
Erik Hernández received his BS and MS degrees in electronic engineering from ESI of Navarra University in 1999. He then joined Tecnun’s RF Integrated Circuit Design Group, San Sebastián, Spain. He obtained his PhD degree in monolithic voltage-controlled oscillators for RF applications in December 2002, after which he joined the Gipuzkoa Center for Technical Research (CEIT) as an associate researcher. His main interests include the design and characterization of passive components and mixers in standard low cost technologies. He can be reached via e-mail at email@example.com.
Roc Berenguer received his BS and MS degrees in electrical engineering from ESI of Navarra University in 1996. In 1999 he joined CEIT as an associate researcher. He received his PhD degree in 2000. His research interests include CMOS and BiCMOS RF circuit design for low cost and highly integrated front-ends.
Jaime Aguilera received his BS and MS degrees in electronic engineering from ESI of Navarra University in 1999. He then joined ESI as an associate researcher. In March 2002 he joined CEIT and a month later received his PhD degree. During this period he also worked on several RF projects for Infineon Technologies, Austriamicrosystems and Xignal Technologies. In December 2002 he joined Modis International to work for Philips Research labs in Eindhoven (The Netherlands). He is currently working on software implementation for RFIC optimization in Philips IC design flow.
Josu Ibarguren is a PhD candidate and is currently working on power amplifier linearization techniques for 3G systems (UMTS – WCDMA) for base stations and repeaters. He has also worked on remote control applications for cranes.
Iñigo Gutierrez received his degree in industrial engineering in 1998 and is currently a PhD candidate. His research interests include the design and characterization of passive elements for RF applications.