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The need for broadband wireless access (BWA) has long been acknowledged as the next step in the evolution of Internet access. Unfortunately, the lack of robust technology at a competitive price has been a barrier to its implementation. Today, though, momentum to cross the chasm is gathering—early adopters have endorsed the technology in under-served rural areas of the world, while standardization efforts have reduced costs enough that mainstream users can now consider WiMAX a viable alternative for broadband access with a future promise of mobile access.
WiMAX, based on IEEE 802.16 specifications, supports operation in multiple frequencies and multiple air standards. To ensure interoperability between multiple WiMAX solutions, the WiMAX Forum, an industry consortium, has developed profiles that specify the operating frequency, bandwidths, air-interface and medium access protocols. These profiles are based on a 256-carrier orthogonal frequency division multiplexing (OFDM) air interface for fixed/nomadic operation, and scalable-OFDM-access (S-OFDMA) air interface for portable/mobile applications.
Figure 1 shows a block diagram of a traditional WiMAX system. An RF transceiver is connected through a power amplifier (PA) and RF switches to the antenna on one side, and to a digital baseband (DBB) on the other. The interface between the RF transceiver and the DBB is composed of analog signals, which can be at intermediate frequency (IF) or baseband. Note that the ADCs and DACs in this architecture can be discrete devices, or can be integrated on an ASIC.
In some applications, a two-chip solution may have higher performance and lower cost than a single-chip solution. The key is to know how to divide the functions between the two chips to best exploit both the circuit topology and the available manufacturing technologies. Smart partitioning does just this, allowing an RF system-on-a-chip (SoC) to provide a complete RF-to-bits solution including all required automatic gain control, transmit power control and RF calibration loops. Including control loops on the radio front end enhances ease of use, provides for an easier mix-and-match capability with different DBB modems and improves performance. The accompanying reduction of real-time software control results in simpler system design. All analog and RF specific controls are integrated on the RF front-end IC. This is smart partitioning. Figure 2 illustrates a block diagram for a system using smart partitioning.
For communication systems such as WiMAX and BWA, consumer prices less than $100 are essential. In CPE equipment for asymmetric digital subscriber loop (ADSL) and 802.11g Wi-Fi ($20 to $30), for example, volumes increased dramatically as prices declined. Emerging markets such as WiMAX are also experiencing similar price pressures. End-user CPE prices are expected to be less than $100 by mid-2007. To achieve these targets, chipset pricing must fall to $20 or $25. Much lower than the current cost, this reduction will require significant improvements for market prices to yield an acceptable profit.
Smart partitioning offers the opportunity to dramatically reduce the total cost of a WiMAX system. Today’s traditional DBBs are mixed-signal ASICs, with over 90 percent of their area occupied by digital gates and 5 to 10 percent used for data converters. The cost to manufacture such a mixed-signal device is over 1.5 times the cost of manufacturing a digital-only IC. The major contributors include higher wafer price (1.2 times), higher test cost (1.1 times), higher yield cost (1.1 times) and larger die size (1.05 times), totaling a 1.5 times increase in cost.
In addition to the tangible cost, there is a large opportunity cost incurred. Data converters typically lag behind by one generation of the process, and proven cores for 90 nm or 65 nm are not available for integration on today’s fine-line digital processes. The opportunity cost for using a 130-nm process for the digital baseband instead of a state-of-the-art 90-nm process can be up to twice. Data converters integrated on a DBB constrain the cost, keeping the IC from taking advantage of Moore’s law.
By itself, the integration of data converters is not sufficient for smart partitioning. The data converters required for WiMAX are typically over-sampled, so handling the raw data rate in and out of the transceiver would present implementation challenges. However, integrating decimation and interpolation filters on the transceiver allows the interface speed to be reduced. The availability of mature fine-line RF CMOS processes, coupled with advances in analog and RF modeling capabilities, have now made it possible to move data converters and other mixed-signal blocks to the RFIC in WiMAX radio designs. For cost and power efficient implementation of the digital blocks, fine-line CMOS is a definite plus. This article explores the choice of digital interface and the ease of use advantages introduced by simple RF drivers for receivers and transmitters.
The evaluation board design and layout has a critical impact on the performance of the mixed-signal component of the DBB. The analog I/O on the reference board is sensitive to external noise, and the supply routes to the mixed-signal portion of the design require high isolation. Eliminating the analog I/O minimizes these noise-coupling issues, and solves the problem of interfacing analog cores from different vendors (such as RF chip and mixed-signal converter cores). For example, some ADC cores require a discrete 5 V driver op-amp to obtain specified data sheet performance. Modems using smaller processes, such as 130 nm or 90 nm, must reduce the signal swing and match the common-mode level to that of the RFIC. These considerations require valuable engineering resources. For systems using smart partitioning, the boundary between the transceiver and the DBB is digital, simplifying these issues.
Two basic options for selecting a digital interface are a high speed serial data stream using low voltage digital swing (LVDS) signaling, or a slower speed parallel bit stream. Variations of these schemes include embedded clock, synchronous clocking, or nibble transfers. Each approach has its advantages and disadvantages.
High speed serial links (see Figure 3) have a lower pin count, reduced switching noise due to the differential signaling and larger separation (between DBB and RF transceiver). However, the high speed circuit design risk is one of the biggest implementation challenges. Implementation of the serializer and de-serializer is complex and requires clock recovery circuits and other custom design blocks that are not readily available in standard digital libraries.
The parallel bit stream approach offers lower data rates and a standard CMOS I/O, but increases the pin count. To reduce the pin count to a manageable number, the data bus can use time duplexing to multiplex between receive and transmit data. Additionally, the I/O can be single-ended if the switching and high frequency noise are carefully managed and isolated from the highly sensitive RF circuitry. The design on the DBB is straightforward, and can be implemented with a standard hardware description language (HDL)-based design flow.
The JEDEC Committee (JC-61), formed in 2002, was chartered to create an open standard for digital interface, enabling smart partitioning and multi-vendor solutions. The published standard, JESD96, offers the high speed LVDS approach. A proposal and basic configuration for the parallel interface have also been accepted. Figure 4 shows an example of a parallel interface implemented on Analog Devices’ AD935x family of smart partitioned transceivers. The ADI/Q™ digital I/Q interface provides the basis of the JC-61 parallel standard.
In addition to ADCs and decimation filters, smart partitioned transceivers also integrate the automatic gain control (AGC) circuitry on the transceiver. The AGC adjusts the gain of the receiver path such that the input signal to the ADC is maximized in scenarios with and without interference. The AD935x receiver signal chain is illustrated in Figure 5.
Time division duplexing (TDD), the preferred system for the future, supports framed waveforms (bursts). The media access controller (MAC) at the base station generates a downlink frame, which starts with a preamble, and follows with a frame control header and multiple data frames. The duration of each frame is short (1 to 2 ms). The input power during the burst varies by 3 dB for fixed systems and 10 to 12 dB for mobile systems.
The transceiver uses the frame preamble to lock the gain of the receiver (see Figure 6). The preamble is one or two OFDM symbols consisting of multiple tones whose phases are aligned to create a waveform with a small peak-to-average power ratio. The tones are also distributed such that the waveform is repetitive in the time domain.
To detect the minimum desired signal, the receiver gain is set to maximum. The in-channel received power is measured at the outputs of the ADCs and decimation filters. The peak detectors distributed along the receiver chain and the ADCs are also monitored for over-ranging. If detected, the receiver gain is reduced depending on the type of over-ranging. If the baseband peak detector before filters indicates clipping, for example, then the LNA gain is stepped down. The AGC algorithm cycles through these iterations and converges on an optimum gain setting. The system then freezes the gain for the remainder of the frame. For the modem to synchronize and correlate to the signal, the receiver gain must be fixed. A fast AGC lock time allows the modem more time to synchronize and make accurate channel estimates, reducing the implementation loss and improving the system performance.
Traditional systems achieve this by distributing the AGC function on both modem and transceiver. The dotted line in the receiver architecture indicates the functional partitioning. In this approach, the DBB must monitor the gain, detect peaks and set a new gain. The algorithm is generally implemented in the RF software driver. Every time the gain is changed, the transceiver must be recalibrated and the DC-offsets must be removed. The RF driver must maintain accurate timing and must respond to interrupts generated from the transceiver, making optimization a tedious, time-consuming task. In the case of multiple vendors, each RF driver must be customized for a specific transceiver. In multiple instances, vendors have struggled to achieve 64QAM operation on their reference designs because of these complex interactions.
A transceiver using smart partitioning integrates the complete control loop including monitoring and control algorithms on a single device. The basic process to lock the gain remains the same, but the responsibility for control is transferred to the RF transceiver. From the modem’s perspective, the loop is autonomous and does not require any dynamic interactions. The modem can still accurately start and stop the loop, and can still monitor the received signal strength indicator (RSSI) and gain settings. All internal calibrations are now self-contained.
With well-managed timing constraints, this smart partitioning approach results in two advantages: a simpler RF driver and shorter AGC locking time. Figure 7 shows that the AGC lock time, when using the autonomous AGC loop on the AD935x, is of the order of four microseconds for an 802.16 waveform. Further advanced techniques such as stronger signal detection, radar detection and interference back-offs can also be easily implemented.
Advanced systems, operating in mobile environments with fading channels, multiple antennas and beam-formed signals, require new techniques such as symbol-to-symbol AGC. The power variation within a burst in this scenario is 9 to 12 dB. A typical power variation versus time for a beam-formed or space-time coded waveform is shown in Figure 8. To accommodate this power step, one option is to increase the ADC dynamic range and pay the corresponding cost of increasing a bit in performance. Another option is to reacquire lock on a symbol-by-symbol basis. A fast AGC with short lock times, coupled with accurate timing control for starting and stopping the AGC loop, could enable symbol-to-symbol AGC.
Figure 9 shows a plot of receiver input vs. measured receiver error vector magnitude (EVM) for a WiMAX transceiver, using smart partitioning along with a software modem implemented with Agilent VSA software. The performance curve exemplifies the ease of implementation achieved using the smart partitioning approach. For low input power, the receiver gain is automatically adjusted to accommodate the small input signal; the gain is then backed off automatically until the EVM is limited by the linearity of the transceiver.
The 802.16 standard specifies a ranging process that determines the correct output power radiated by the terminal. This process ensures that transmissions from multiple terminals arrive at the base station at the desired power level (within a certain range that can be handled by the base station). The standard specifies a transmit power control range of 50 dB for the terminal. This will allow terminals to be distributed around the cell site to meet the equal power criteria at the base station.
During the ranging process, the base station requests the terminal to send out a ranging signal. The base station will then command the terminal to increase or decrease its transmit power. The WiMAX Forum is currently discussing requirements for accuracy and number of iterations.
In traditional architectures, external attenuators and true rms power detectors can be used to achieve the system specifications. Using smart partitioning, the integrated ADCs and DACs offer the transmitter the ability to rapidly measure highly accurate burst output power. Figure 10 shows the components of the unique transmit power control scheme implemented on the AD935x transceiver. To utilize the power detector, the transmitted signal is sensed from an external coupler. It is then fed back to the receiver, where it is down-converted to baseband. The receive ADCs digitize the signal, which is then processed by a digital rms power meter block. This takes advantage of the half-duplex nature of the system to make an accurate measurement using the idle calibrated receiver path. The detector is capable of measuring power on a TX burst-by-burst basis, providing the modem with near-real-time power information. The front-end mixer is designed to be temperature and frequency independent, and thus requires only a one-point factory calibration. This feature saves test time and reduces calibration complexity.
The ease of use advantage is equally applicable to the transmitter. The modem can vary the power on a burst-by-burst basis by simply writing to the register before the burst. The transmit power is automatically adjusted to the open loop accuracy specification of the device. If greater accuracy is required, the transmit power control loop can be initiated and a correction factor can be applied to the next burst. Other novel techniques such as self-generated short test signals can be transmitted before the actual burst to calibrate the device in close loop. These techniques can be explored as emissions requirements and system requirements evolve.
The smart partitioning of a WiMAX system enables the lowest system cost and reduces the dependence of real-time control from the DBB. Integration of the ADCs and DACs by itself is not sufficient to achieve these advantages. To reduce the speed of the digital interface, decimation and interpolation filters are also integrated in the transceiver. These stages also include the channel filters. A large portion of the RF driver complexity is managing the real-time signaling between the modem and transceiver to achieve fast and accurate AGC and TPC. To reduce the processing load on the modem, the AGC and TPC algorithm blocks are integrated on the transceiver. Other smart features can be integrated on the transceiver such as auxiliary ADCs and DACs, RF general-purpose outputs for RF switch and PA control. The AD935x family of transceivers exemplifies the RF system-on-chip features that can be implemented.
Noman Rangwala received his bachelor of engineering degree from Victoria Jubilee Technical Institute, Mumbai, in 1992, his MSc degree from the University of New Mexico, Albuquerque, NM, in 1994, and his MBA degree from San Diego State University, San Diego, CA, in 2000. He is a marketing manager with responsibility for WiMAX transceiver marketing within the High Speed Signal Processing division of Analog Devices Inc. (ADI). He also has over six years of experience in IC design and development.
Richard H. “Rick” Myers received his BS degree from Old Dominion University in 1983. He is a senior applications engineer focused on wireless applications for the High Speed Signal Processing division of Analog Devices Inc. (ADI) and is based in Raleigh, NC. Before joining ADI, he was CDMA hardware development manager for handsets at Ericsson in Research Triangle Park, NC, and principal electrical engineer of RF and receivers at E-Systems (Raytheon) in Falls Church, VA.
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