advertisment Advertisement
This ad will close in  seconds. Skip now
advertisment Advertisement
advertisment Advertisement
advertisment Advertisement
advertisment Advertisement
Industry News / Passive Components / Test and Measurement

RF Coplanar Probe Basics

Explanation of the construction, characteristics and usage of coplanar waveguide probes

March 1, 2003
/ Print / Reprints /
| Share More
/ Text Size+

Coplanar waveguide probes, also referred to as coplanar probes, are the method of choice for launching RF signals on and off a wafer. This article explains their construction, RF characteristics and proper usage. Before the advent of coplanar probes, finding the RF behavior of a die on a wafer was a complicated process. First the wafer was diced and an individual die mounted into a test fixture (see Figure 1 ). Only then could the die's (and, more generally, the wafer's) RF performance be known. Fixturing involved attaching the die to a PCB, wirebonding to the bond pads, connecting RF cables to the fixture and measuring. Discriminating between the die's and the fixture's responses became a central issue. Furthermore, fixturing die is a time-consuming process, making it impractical for high volume screening. Thus arose the need for on-wafer characterization.

Some on-wafer devices are active (such as transistors and diodes), while others are passive (such as resistors, inductors and capacitors). Electrical models of the devices are obtained from RF measurements made on-wafer. Since circuits are designed with these models, it is important that the on-wafer characterization be accurate. Calibration is only the first step. Afterwards, de-embedding must be performed to obtain the RF performance of the on-wafer device-under-test (DUT).

Mechanical Construction

Figure 2 shows a typical construction for a coplanar probe. The tips are made of flexible beryllium-copper (BeCu) to keep them from digging into the die's probe pads.1 BeCu is optimal for probing gold pads on fragile GaAs wafers. Not only is it flexible, it also offers low contact resistance. On the other hand, tungsten (W) tips are firmer, breaking through the oxide film on aluminum pads to make good electrical contact. During test, aluminum oxide buildup can vary the contact resistance. While excessive over-travel of the probes can break through the oxide, it causes the probes to wear out sooner. Furthermore, the pads must be larger to accommodate skating, and large probe pads add parasitics to the measurement. Another drawback to tungsten is that its contact resistance increases with use. With either BeCu or W, the contact pressure has a significant effect on the probe's durability, especially with W because of its stiffness. The springy compliance of individual ground and signal probe tips becomes a real advantage when probing non-planar wafers and packages.

The probes are gold-plated to reduce conductor loss. Nickel underplating keeps the gold from rubbing off, yielding longer probe life. When biasing the DUT, the probe should be able to withstand high DC currents.

Using Coplanar Probes

When a coplanar probe wears out, the tips are often no longer in the same plane. For example, consider the ground-signal-ground (G-S-G) probe shown in Figure 3 . Two 100 Ω resistors in parallel produce a 50 Ω load. If only one of the ground probes touches, then the load will appear as 100 Ω. A more subtle point is that the reference plane at the probe tips is no longer in a straight line. Poor reference plane definition will introduce uncertainty in the DUT measurement.

The springy compliance of individual signal and ground probe tips becomes a real advantage when probing non-planar surfaces on wafers and packages. However, this can be a drawback. Since each probe tip is independently flexible, any reference plane configuration is possible. The best way to check probe tip planarity is with a contact substrate. The contact substrate is simply a metallized field. When the probes are lowered onto this field, the probe tips leave scratches or "footprints" in the metal (see Figure 4 ). The scratch depth indicates when the probe is tilted or mounted at an angle. Another method for checking probe planarity is by using an ohmmeter. To do this, short the signal and ground probe tips by pressing them to the contact substrate, verifying both probes are touching. If they are not touching, an open will register on the ohmmeter. Of the two methods, looking at the probe tips through a microscope is preferable to blindly observing its electrical response.

Some probe micropositioners offer a planarity adjustment. If this is not available and one side of the probe is seen higher than the other, then metal shims placed under one side of the probe will elevate it.

To measure die on opposite sides of the same wafer requires precise alignment of the wafer and probe. The probe tips should line up to an edge of the die, forming a plane. If the wafer is oriented at an angle to the probes, then moving a distance across the wafer will not land the probe tips on another die's pads.

To align the probes and the die, the wafer chuck can be swept from left to right, observing an edge of the die as it scans. If the probe tips are not evenly aligned with the wafer, then the edge will appear to rise and fall. The theta rotation of the chuck can be adjusted until the die's edge sweeps across the wafer in a straight line. When wafer scanning is not possible, the outer corners of a die can be used for alignment. The outer corners of the probes will define the reference plane.

When a coplanar probe initially touches down on a probe pad, the tip arrives normal to the wafer surface. Yet because the probe's body is at an angle to the wafer, lowering it further causes the tip to glide across the pad. This phenomenon is known as skating. Some skating is always necessary since the signal and ground pad metal may not be deposited with the same thickness on all wafers. In some instances, the surface of a wafer may not be planar, especially when multiple dielectric and metal layers are used. Chemical-mechanical polishing (CMP) during IC processing leaves each layer with ±0.5 μm flatness across the wafer.

When designing the die, alignment marks near the die's pads help to align the coplanar probe for a consistent amount of over-travel. Triangular alignment marks designed for a 1-mil probe skating are shown in Figure 5 . The marks ensure that the probes stop at an exact spot on the standards corresponding to the calibration coefficients entered into the VNA.

Skating has both a mechanical and an electrical impact on the measurement. Mechanically, skating leaves conspicuous marks on the die pad, visible under a microscope. These marks tell when a die has been probed, useful in post-probe inspection. A disadvantage is that the scrubbing action of the skating scrapes some metal off the pads. Over time, it accumulates on the probe tips, requiring periodic cleaning. Electrically, pad over-travel resembles an open stub (see Figure 6 ). An open stub attenuates an RF signal at higher frequencies. Different amounts of skating can mistakenly resemble nonlinear behavior in the DUT.

The equivalent circuits of a pad stub and of the probe with a pad stub are shown in Figure 7 . The interaction of the stub and the probe can be quantified by using the following method. First a thru - reflect - line (TRL) calibration is done using an alumina calibration substrate. Then another through measurement is performed on the wafer with probe pads. An offset delay is used to shift the reference plane to where the probe pad meets the thru line. An RF measurement will then quantify the probe pad to a probe tip electrical model. The results of this measurement can be fitted to the equivalent circuit model.

During calibration, getting the probes to contact the exact same place on the calibration standards each time is difficult. A common mistake is to readjust the probes when moving from one calibration standard to another. Before calibration has begun, the micropositioners must be set once and their position not changed during calibration. Movement of the probes changes the standard's parasitics, particularly the inductance (see Figure 8 ). With coplanar probes, the amount of inductance depends on the amount by which the probe overlaps the standard.

In general, too much skating shortens the length of the calibration standards. With the thru standard, the reference plane is no longer centered in the middle. Excess skating makes the delay entered into the VNA to be too long, causing the reference plane of each port to overlap with the other. To verify the effect of excessive overlap, the open standard must be remeasured after calibration. The return loss should not be more than 0 dB. If this is the case, then the load measurement may have had too much skating.

After extended use, the probes accumulate debris such as lifted probe pads or metal strings from around the pads. Probes can be cleaned with either compressed air or isopropyl alcohol (IPA) applied with a swab. The swab should have a sponge tip rather than cotton, which can leave threads behind. The wiping should always be done in a direction away from the probe tip. IPA can flow into cavities in the probe. Since these cavities are not directly exposed to air, it can take some time for them to dry (often 15 minutes or more). As they dry, the RF measurement of an open will change with time.

Another method of cleaning uses an alumina substrate. Lightly bouncing the probe tip onto a smooth, non-metallized area of the substrate will knock debris off the tip. A gel pack can be used in a similar fashion. A gel pack is a small plastic package with gelatinous, sticky material inside, used to store die or small components. Lowering the probes onto the gel pack will stick the debris to the gel.

Some probe stations have a vibrating scrub pad that is near the wafer chuck programmed to scrub a needle probe when a number of bad die are measured in a row. Scrub pads are typically used with needle probes and should be applied judiciously to coplanar probes. The scrubbing action wears out the probes faster.

Probe Configurations

The most popular coplanar probe configuration is the ground-signal-ground (G-S-G) probe. Two ground probes shield a single signal probe in-between. Its principal advantage is in tightly controlling the fields around the signal probe. Electric fields emanating from the signal (S) probe terminate on the ground (G) probes, while the magnetic fields between S and G cancel. For example, consider probing two 100 Ω resistors in parallel which equate to a 50 Ω load (see Figure 9 ). In this case, the mutual inductances M on either side of S are balanced due to equal current division between the grounds.

Now consider the case of an unbalanced load where the ground currents are not evenly split (see Figure 10 ). Such an imbalance might be intentional to emulate the current flow in a DUT. While the parallel-equivalent load is still 50 Ω, this imbalance introduces small errors in the calibration. The probe's parasitics will not equal those in the balanced current case. Since the VNA calibration coefficients are designed to correct for balanced currents, using the unbalanced load can add error to the calibration. Unbalanced currents give rise to higher order modes that can cause oscillations in a DUT. To overcome this, the DUT should be redesigned for balanced current loading or the calibration load redesigned to emulate the load presented to the DUT. Differences in the DUT and calibration currents can make a difference when measuring minuscule amounts of capacitance and inductance such as in device modeling.

Compared to G-S-G probes, signal-ground-signal (S-G-S) probes suffer from crosstalk and poor isolation. Inductance in the shared ground probe serves as a coupling path between the two signal probes. To quantify the G probe's inductance, contact the probes to a shorting bar and measure the insertion loss between the two signal probes. In general, S-G-S probes are best used below 10 GHz.

The principal advantage of an unbalanced probe (ground-signal or signal-ground) is in reducing the overall die size. One less pad means a slightly smaller die, thereby increasing the number of die per wafer. The drawback is that one less ground probe means less shielding, resulting in crosstalk problems (see Figure 11 ). A second ground probe on the other side of the signal probe ensures a better-controlled mode of CPW wave propagation along the line as compared to G-S (or slotline) propagation. Even calibrated, the right side of the unbalanced probe can couple to the substrate, limiting its high frequency response. An unbalanced probe should not be used on balanced probe pads. In such a case, the unused ground pad will behave as an RF open stub in the ground path's equivalent circuit.

G-S-G probes can also have an unbalanced design. The distance between probe tips (referred to as the pitch) need not be equal on both sides of the signal probe. The RF performance degrades as the pitch on either side becomes more unequal.

Both balanced and unbalanced probes are considered single-ended, also known as using a common-mode. In common-mode circuits, the signal voltage is referenced to ground. Conversely, signals on differential lines are referenced to one another. In general, differential circuits exhibit better crosstalk immunity and dynamic range than ground-referenced circuits.

One way to convert a single-ended probe to a differential probe is to install a 180° splitter-combiner balun (see Figure 12 ). The signal will propagate between the pair of lines as opposed to between the signal and ground. In principle, the same calibration techniques apply to differential probes. However, measuring differential S-parameters may require a VNA with twice as many ports. Performing a calibration requires twice as many standards and the error model is twice as large.2-3

Conductive vs. Insulating Substrates

A brief coverage of wafer types and their RF properties helps to understand why de-embedding the wafer's parasitics is so essential. Most substrates are made of either silicon (Si) or gallium arsenide (GaAs). These substrates are either semi-insulating or semi-conductive, depending on the doping. Lightly-doped silicon substrates have resistances around 10 kΩ-cm. This is significantly below what is achievable with lightly-doped GaAs (10 MΩ-cm).

Understanding the wafer's loss mechanisms helps to understand the RF behavior of a die on the wafer. In bulk semiconductors, there are two types of losses, ohmic loss and polarization loss. The loss associated with the carriers traveling through a semiconductor is ohmic loss. The dielectric polarization of the substrate has a frequency-dependence, leading to a frequency-dependent polarization loss. At low frequencies, ohmic loss dominates, while at high frequencies polarization loss does.

These losses, along with the skin effect, impact the RF performance of the conductors on the wafer. The skin effect sets up a current return path just below the surface of the substrate (see Figure 13 ). The degree of return (or image) current flowing along the wafer surface depends on the conductivity of the substrate.4 Interestingly, more ground return current can flow along the substrate's surface than through the coplanar ground conductors. In such cases, the skin losses in the substrate will be larger than the losses in the ground conductor.

In general, the transmission line loss depends on the line width, the substrate's properties and the thickness of the insulating layer (SiO2 or polymide) between the metal layer and the Si substrate.5 For example, a coplanar waveguide on a conductive silicon substrate with a thick polymide insulating layer can yield minimal transmission line attenuation.6

During IC processing, an insulating oxide layer is deposited between the substrate and the metal. When the metal-insulator sandwich contacts the substrate, either an accumulation, depletion or inversion layer forms on the semiconductor surface, depending on the surface potential. Even when the bulk resistivity of the semiconductor is high, the resistivity on the substrate surface can still be low. With conductive substrates, the electric field is concentrated in the oxide above the substrate's surface, giving rise to a large distributed Cox. Since the substrate itself has a low resistance, both Rsub and Csub within the semiconductor are small.

High frequency losses are directly related to the field penetration into a semi-insulating substrate. At high frequencies, multiple modes of electromagnetic propagation can be launched in the substrate.7 When the electric field does not penetrate deeply into the substrate, a surface wave mode can arise at higher frequencies. With semi-insulating substrates, the electric field penetrates deeper into the substrate as the frequency increases, establishing a quasi-TEM mode.

A way to quantify the substrate's loss is with a simple transmission line model. With transmission lines, the loss can be expressed through the relative dielectric constant εr. The insulating oxide layer between the line and the substrate lowers εr, lessening the line's loss. Because the oxide layer increases the conductor-substrate separation, electromagnetic fields in the substrate will not be as strong.8

Conductive substrates are lossy and their conductivity is frequency-dependent, so characterizing devices can be difficult. On a conductive silicon substrate, wide transmission lines often have more high frequency loss than narrow lines.9 This characteristic is especially problematic for calibration methods that rely on the characteristic impedance Z0 of a transmission line.10 Conversely, the high resistivity of semi-insulating GaAs leads to less RF transmission line loss than on semi-insulating silicon. Whether semi-insulating or semi-conducting, a silicon substrate's resistivity increases rapidly with frequency. Hence, its transmission line loss increases in the same manner.

Probe Pads and Interconnecting Lines

IC fabrication engineers are interested in the intrinsic characteristics of the device, such as the doping levels, the diffusion depth and the junction depths within the wafer. Capacitance, resistance and inductance measurements are the best ways to reveal these characteristics. Placing the coplanar probes directly on the device to be measured is not possible. Probe pads and interconnect lines leading to the DUT are required. The disadvantage is that the parasitics of the pads and interconnects can be larger than the measured parameters of the device itself.

The calibration procedure defines the reference plane at the probe tips. To de-embed the probe pads and interconnects, and find the intrinsic DUT's RF behavior, the electrical reference plane must be shifted from the coplanar probe pads to the DUT. To illustrate the impact of the pads and interconnects on the device measurement, consider h21, the current gain of a transistor with a shorted output, defined as

h21 = y21/y11 (1)

Any parasitic capacitance will affect the measured admittances y21 and y11, so de-embedding the probe pads and interconnects is critical to obtaining an accurate h21 measurement. Failure to do so can impact each of the four S-parameters (S11...S22) by 1 to 2 dB. This error is compounded when the S-parameters are used in complex calculations, making transistor benchmarks such as fT and fmax appear as much as 25 percent lower than they actually are. The impact of the pads and interconnects becomes larger as the device's dimensions get smaller, particularly with conductive substrates.

Figure 14 shows a typical bond pad and interconnect scheme. The bond pads are on top of a low loss dielectric insulating layer, either oxide or polymide. A first-order electrical model of the substrate, good for frequencies less than 3 GHz, is also shown. The value of the high Q capacitor Cpad can range from 0.1 to 0.3 pF, depending on the dielectric material and the substrate's thickness.11 The resistor Rpad depends on the substrate's resistivity. In the bottom diagram, the values of the resistors depend on the amount of resistive coupling through the substrate, while the capacitors depend on the fringing fields between the pads and the interconnects.

Some Points to Consider When De-embedding

Here are some points to consider when laying out probe pads and interconnecting lines. The probe pads should be as small as possible to reduce capacitance to the ground and to nearby interconnects. To isolate the interconnecting lines from the underlying substrate, the wafer oxide should be as thick as possible (for instance, a field oxide). The substrate should either be highly conductive (to reduce resistance to the backside ground) or highly insulating (to behave principally as a dielectric). The choice of conductivity depends on the circuit application and layout.

The ground traces on the surface should have low inductance.12 The DUT area reserved should be as small as possible, no bigger than the biggest DUT to be characterized. The thru structure used in de-embedding will then be no longer than necessary.

Because open, short and thru dummy structures used in de-embedding have no DUT, the parasitics of the substrate are somewhat different than with an active device implanted. For best results, the substrate used for the de-embedding structures should be the same as the DUT. Specifically, the doping levels, the epi layer and the overall wafer thickness should be the same as for the DUT, so that the substrate's parasitics are properly de-embedded. Designing the probe pads and interconnects for high isolation can help overcome substrate differences between the DUT and de-embedding structures.

Electrically, the ideal probe pad exhibits a small capacitance to ground and a low conductor resistance, made possible with a small pad size and a thick oxide layer. To further decrease the substrate capacitance, insulating trenches cut deep into the epi and filled with field oxide can be placed directly underneath the probe pads.

What ultimately determines the pad size is the probe, not the wafer fabrication process. Probe over-travel on the pad as well as the width of the probe tip decide the minimum pad allowed. Employing a 50 µm probe over-travel is common. With membrane probes, even smaller pads are possible since skating is not a factor.

The contact resistance changes every time the probe contacts the pad.13 While the amount of change is small, it can make an impact when de-embedding minute quantities. Specifically, the equivalent circuit values of the pads and interconnects should not be less than the repeatability of the probe contact.

To find the equivalent circuit of the pad and interconnects more easily, a layout should be designed where the major parasitics are easily identifiable and dominate. This makes the modeling task easier while large, dominating elements make it more accurate. At frequencies below a few gigahertz, the series impedance of the interconnects is low. In such cases, the Z terms can be ignored. Capacitance is small when the interconnects and pads are not close together or when the substrate is semi-conductive.

Sometimes, calibration is performed with open pads instead of lifting the probes up in the air. When verifying with probes in the air, an open-pad calibration will appear to have gain. This is due to a lack of inductance in the air compared to the open pads.

Care should be taken when attempting time-domain techniques to shift the reference plane from the probe pads to the DUT. Probe tip placement on the pads inevitably varies, and with such small distances the electrical reference plane can easily be shifted into the DUT.


This article provides the reader with insight into the design and proper use of RF coplanar probes. Sufficient details are given to develop an understanding of its electrical behavior to enable more accurate measurements. Theoretically, on-wafer measurements should yield the same results as those made using a test fixture, the functional difference being CPW probes instead of RF launchers and interconnects. While coplanar probes avoid many of the parasitics found in test fixtures, similar issues arise. Coplanar probes cannot contact the DUT directly, so probe pads and interconnects must be de-embedded, not unlike de-embedding the launchers and interconnects in a test fixture.


1. J. Carbonero, G. Morin and B. Cabon, "Comparison Between Beryllium-copper and Tungsten High Frequency Air Coplanar Probes," IEEE Transactions on Microwave Theory and Techniques , Vol. 43, No. 12, 1995, pp. 2786-2793.
2. D. Bockelman and W. Eisenstadt, "Calibration and Verification of the Pure-mode Vector Network Analyzer," IEEE Transactions on Microwave Theory and Techniques , Vol. 46, No. 7, 1998, pp. 1009-1012.
3. D. Bockelman and W. Eisenstadt, "Pure-mode Network Analyzer for On-wafer Measurements of Mixed-mode S-parameters of Differential Circuits," IEEE Transactions on Microwave Theory and Techniques , Vol. 45, No. 7, 1997, pp. 1071-1077.
4. J. Zheng, V. Tripathi and A. Weisshaar, "Characterization and Modeling of Multiple Coupled On-chip Interconnects on Silicon Substrate," IEEE Transactions on Microwave Theory and Techniques , Vol. 49, No. 10, 2001, pp. 1733-1739.
5. B. Kleveland, T. Lee and S. Wong, "50 GHz Interconnect Design in Standard Silicon Technology," IEEE Microwave Symposium Digest , 1998, pp. 1913-1916.
6. G. Ponchak, A. Margomenos and L. Katehi, "Low Loss CPW on Low Resistivity Si Substrates with a Micromachined Polymide Interface Layer for RFIC Interconnects," IEEE Transactions on Microwave Theory and Techniques , Vol. 49, No. 5, 2001, pp. 866-870.
7. H. Hasegawa, M. Furukawa and H. Yanai, "Properties of Microstrip Line on Si-SiO2 System," IEEE Transactions on Microwave Theory and Techniques , Vol. 19, No. 11, 1971, pp. 869-881.
8. A. Reyes, S. El-Ghazaly, S. Dorn, M. Dydyk and D. Schroder, "Silicon as a Microwave Substrate," IEEE Microwave Symposium Digest , 1994, pp. 1752-1762.
9. S. Zaage and E. Groteluschen, "Characterization of the Broadband Transmission Behavior of Interconnections on Silicon Substrates," IEEE Transactions on Components, Hybrids and Manufacturing Technology , Vol. 16, No. 7, 1993, pp. 686-691.
10. Williams and R. Marks, "Accurate Transmission Line Characterization," IEEE Microwave and Guided Wave Letters , Vol. 3, No. 8, 1993, pp. 247-249.
11. N. Camilleri and J. Kirchgessner, "Bonding Pad Models for Silicon VLSI Technologies and Their Effects on the Noise Figure of RF NPNs," IEEE Microwave and Millimeter-wave Monolithic Circuits Symposium Digest , 1994, pp. 225-228.
12. T. Kolding, "On-wafer Calibration Techniques for Gigahertz CMOS Measurements," IEEE International Conference on Microelectronic Test Structures , Vol. 12, 1999, pp. 105-110.
13. G. Carhon, B. Nauwelaers, W. De Raedt, D. Schreurs and S. Vandenberghe, "Characterizing Differences Between Measurement and Calibration Wafer in Probe Tip Calibrations," Electronics Letters , Vol. 35, No. 13, 1999, pp. 1087-1088.

Post a comment to this article


Forgot your password?

No Account? Sign Up!

Get access to premium content and e-newsletters by registering on the web site.  You can also subscribe to Microwave Journal magazine.


advertisment Advertisement