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Industry News / Semiconductors / Integrated Circuits / Software & CAD / Test and Measurement

Calculation and Measurement of Lock Time in a Phase-locked Loop Frequency Synthesizer

Presentation of the equations involved in predicting lock time and transient response of synthesizer phase-locked loops

April 1, 2002
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Technical Features

Calculation and Measurement of Lock Time in a Phase-locked Loop Frequency Synthesizer

Lock Time is an Important Design Parameter


Florian Krug
Technische Universitaet Muenchen
Muenchen, Germany

Jean Wilwert
Infineon Technologies
Muenchen, Germany

The 'Wireless World' (radio and television broadcast, cordless phones, cellular radio communication, remote controls, wireless computer networking, etc.) has lots of data to transmit and available frequency bands are an extremely scarce resource. Therefore, high spectral efficiency, that is, carrying as much useful information as possible within a given radio bandwidth, is a must for all new services.

Digital transmission allows the removal of most redundant information before going on the air. For the radio transmission itself, two major techniques are currently used. First, a certain number of data channels are transmitted over a single broadband radio channel and separated by the use of individual codes (such as code division multiple access (CDMA)).

The radio channel remains continuously activated and data channels are added and removed as needed in the limits of the radio channel capacity. Data channels may use different radio channels in successive time slots or even simultaneously to increase the transmissible data rate.

Secondly, every data channel uses its own narrowband radio channel. As a single data channel does not continuously need the full radio channel capacity, two or more data channels share a single radio channel. The switching takes place according to a predefined channel and time allocation scheme or on a request-grant basis.

Frequency hopping allocates different radio channels to a single data channel in successive transmit/receive time slots. It helps to reduce the information loss due to selective fading up to extinction as well as interference with uncorrelated emitters and reflected signals. These problems become more and more obvious as transmitters use higher frequency bands. It is also possible to allocate more than one radio channel to a single data channel in order to increase the data rate. In this case the high rate data channel is split and recombined by software so that it can be handled as two or more standard channels by the radio hardware.

Each time a transmitter or receiver changes its radio frequency, the synthesizer must perform a lock process. The frequency difference, and consequently the lock time, can be rather small (two adjacent radio channels) or large (after device power-on). Whereas power-on is less critical (response time is often not much of a problem and even the additional power consumption with larger lock times may be tolerated), the idle time in data transmission imposed by channel switch lock times is of much concern since it reduces the overall channel capacities in terms of bits per second.

Reducing the lock time as much as possible is a major concern in the design of phase-locked loops (PLL). Various design variables in the PLL have an influence on this key parameter. However, it must be considered that other important properties of the loop also depend on them.

The purpose of this article is to present different methods to predict the lock time of a given PLL and to compare the results with actual measurements.

First, a short description of the functional blocks in a PLL is given, the relevant parameters are introduced and some hints on the constraints limiting their variation are offered. Two different methods to determine the expected lock time are presented. Next, two procedures to measure the lock time of a PLL are described. Finally, these results are compared to those calculated when substituting the mathematical variables with the actual numerical values from the hardware.


Fig. 1 Phase-locked loop building blocks.

Short Review of PLL Fundamentals

A PLL basically consists of four functional blocks: a phase detector (PD), a loop filter with low pass characteristic, a voltage controlled oscillator (VCO) and a programmable divider with the variable divider factor N. These blocks are connected, as shown in Figure 1 .

A stable reference signal of frequency fref and the scaled-down output frequency fout /N are compared in the PD, which is actually a phase-frequency detector in most applications. If the phase and frequency of fref and fout /N match exactly, the PD outputs either no signal or a neutral one so that the output voltage level of the loop filter remains unchanged as well as fout . This corresponds to the locked state.

If the PD detects a negative or positive phase or frequency offset between fref and fout /N, it outputs an UP or DOWN signal which drives the filter output voltage higher or lower. This in turn increases or decreases the VCO output frequency fout .

The phase detector itself has a voltage output. Especially in demanding systems, this has some drawbacks which are strongly reduced if the loop filter is driven by current sources and sinks. They are known as charge-pumps. In circuit design, they are separate from the actual PD but, in loop theory, both blocks are regarded as a single unit.1,2

The programmable divider factor N allows the VCO to generate different frequencies with a single fref , which may be generated by a crystal oscillator.


Fig. 2 PPL elements used for calculations.

Figure 2 shows the same PLL in a form used in control theory for calculations in the frequency domain. G(s) is the forward transfer function comprising the individual transfer functions of the PD (with charge-pump), the loop filter and the VCO. H(s) is the feedback transfer function representing the divider as single element. s is the counterpart in the frequency domain of the commonly used variable t in the time domain. Usually, calculations refer to phase rather than frequency (notice that integration of frequency over time yields the phase). qr (s) is the reference phase, qe (s) the error phase between the reference and the divided VCO output signal qi (s) and qo (s) is the output phase of the VCO. Be aware of the plus and minus signs at the summing point.

All calculations of PLL loops in control theory are essentially based on the following Equations:

Open loop transfer function or open loop gain

Closed loop transfer function or closed loop gain:

Where s = jw

Note that the plus sign in the denominator in Equation 2 comes from the minus sign at the summing point.

The type of a PLL refers to the number of poles of the open loop transfer function located at the origin in the root locus plot. Because the VCO acts as a perfect integrator (pole at the origin) every PLL is at least of type 1.

PLLs with passive filters are all of type 1 because these filters do not act as perfect integrators. However, a passive filter in combination with a charge-pump at the output of the PD behaves like a perfect integrator and thus confers type 2 characteristics on the PLL.2 The order of a PLL refers to the highest degree of the polynomial expression (1+G(s)H(s)), which is termed the 'characteristic equation.'

As mentioned before, the VCO makes the PLL to be at least of type 1 and thus of first-order. The (digital) PD and the programmable counter in the feedback branch are not considered as frequency-variable components in the linear circuit analysis. Thus, the filter is the only part to raise the order of the PLL, which makes its order to be higher by one unit than that of the filter. A first-order filter (such as an R-C circuit between the PD/charge-pump output and ground) yields a second-order PLL; a PLL with a second-order filter is itself of third-order, etc.

Textbooks on PLLs present the details of linear control theory for analog second-order systems. The handling of the corresponding mathematics is not too complex and second-order is the highest one which can be treated analytically in all details. In practice there are two problems with this approach.

On the first hand, most synthesizer PLLs are digital, not analog (phase/frequency error evaluation is time discrete) and not linear. However, as mentioned in Gardner2, this is not so much of a concern if the loop bandwidth is small compared to the sampling frequency of the PD.

On the other hand, most systems, especially in modern digital communication components, are of higher than second-order: loop filters of second- and third-order (loops of third- and fourth-order) are common.

All the building blocks of a PLL have an influence on the lock time. But usually the filter is the only part which a system designer can really build to his personal desire. Sometimes the characteristic of the PD/charge-pump (the charge-pump current) can be changed within narrow limits. The reference frequency, VCO frequency and gain, as well as the divider factor N, are fixed by the system's specification and the available components.

Besides lock time, the critical parameters to which a PLL must comply are phase noise and spurious emissions. Unfortunately, shortening the lock time worsens noise and unwanted emissions, and improving the last two properties slows down the lock process. The key parameter to this dilemma is the loop bandwidth, which is mainly fixed by the loop filter, since all other blocks are more or less beyond the reach of the designer.

In short, a small bandwidth means a large lock time but good noise/spurious performance whereas a large bandwidth goes with fast locking, higher phase noise and unwanted emissions. So the designer has to find a compromise which satisfies all requirements as well the lowest possible cost and complexity. This usually means that the more demanding the system, the higher the required order of the loop filter. The transition between the pass-band and cut-off region becomes sharper which allows the pass-bandwidth to be maximized while retaining a high suppression factor for all unwanted frequencies beyond the cut-off.

The drawback with this procedure is that theoretical calculations of the behavior of the PLL rapidly become very complex and even impossible for higher order loops. Thus, it is of interest to know if a simplified model for fast evaluation can be used without losing too much accuracy. The present article shows that this is indeed possible.


Fig. 3 Third-order loop filter.

Lock Time Calculation: Two Important Methods

The first method is based on a second-order control loop approach (PT2); higher order systems are approximated to a second-order. The second method (nth order polynomial) uses no approximation and therefore yields results which are more accurate. However, calculations are very laborious and, for higher than fourth-order, only feasable with numeric approximation that may introduce hardly predictable errors.

Both methods assume a continuous-time linear system approach2 and need the closed-loop transfer function in the frequency domain as a starting point. Therefore, the first step is to determine this function.

The different steps are shown for a fourth-order system, that is, a PLL with a third-order loop filter, as shown in Figure 3 . All frequencies must be expressed as angular frequencies (rad/sec).

To make it easier to handle, the defined shortcuts are

x0 = C2 R2
x1 = C1 C2 C3 R2 R3
x2 = C1 C2 R2 + C1 C3 R3 + C2 C3 R2 + C2 C3 R3
x3 = C1 + C2 + C3

With the transfer function of the third-order filter

s = jw (w is the angular frequency)

The closed loop transfer function Gcl (s) of the fourth- order system is given by

where

kF = phase detector gain
kVCO = VCO gain
N = divider factor

PT2 approximation

The name PT2 stands for a control loop whose characteristic equation can be written in the form of a second-order polynomial, as

s2 + 2 zwn s + wn 2 = 0 (5)

It is relatively easy to calculate the loop characteristics according to the PT2 approximation; for details of theory and practical implementation see Wolaver3 and Banerjee.4 However, as stated above, this method does not give an exact theoretical replication of the real behavior of PLLs of third- and higher order, which are most commonly used.

The approximation is done by ignoring all terms of the denominator Dencl (s) in Equation 4 with an exponent to s higher than 2. This is tolerable since practical values of the filter components (Cx <3 > x1 and x3 >x2 in Gcl (s). Consequently, this denominator becomes

Den'cl (s) = s2 Nx3 + s K F KVCO x0 + K F KVCO (6)

Since by definition the denominator Gcl (s) of a genuine PT2 system represents the left-hand part of the characteristic equation, the variables wn (characteristic angular frequency) and z (damping factor ) can be determined by comparing the coefficients of Equation 6 and the left-hand part of Equation 5. The obtained relations are

Essentially, the remaining angular frequency error vs. time, that is, the difference from the frequency at t®∞ derived from the step response of a PT2 element is described by

A damping factor 0 < z < 1, characteristic for a damped oscillation, is assumed, which is valid for most of the considered PLLs. Dwoff is the frequency jump to be performed and Dw(t) the time dependent frequency error.

Damping factors z = 1 and z > 1 result in different equations, which are somewhat simpler because the system is no longer oscillating. These cases are not treated here.

Equation 7a can serve as the basis of a simulation to graphically determine the lock time as will be shown later. By doing a further approximation that may slightly increase errors already inherent in the PT2 method, it is possible to deduce an equation that allows the direct calculation of the lock time. To this purpose Equation 7a is written in the following form

with

Equation 7b describes a damped sine wave. The lock time tL can be calculated by determining the time span between the start of the lock process (t=0) and the moment when the envelope of this wave reaches a certain (small) value B, that is, the tolerable angular frequency error

This yields the lock time tL (calculated for a specified error angular frequency B)

A similar calculation can be performed with the frequency error functions for z = 1 and z > 1. Without oscillation, tL spans the interval from t = 0 up to the moment when the corresponding error function itself becomes smaller than B.

Nth Order Polynomial Method

This calculation is accurate but it becomes very complex with more elaborate PLL structures, especially loop filters, and the accuracy of the calculations potentially suffers from large numerical errors. The poles of the closed-loop transfer function have to be calculated, which means finding the roots of its denominator.

It is rather laborious to manually calculate the zeros of a third- or fourth-order polynomial (symbolic solution and substitution of the variables by the actual PLL parameters). Alternatively, the job can be done through numeric approximation with appropriate computer software.

Polynomials of an order higher than four cannot be solved symbolically for their zeros. Numerical approximations are inevitable.

For a system with a filter like that shown previously, a VCO gain factor KVCO = 40 106 rad/s, a phase detector gain factor KF = 2.8 10-3 A/rad, a divider ratio N = 6616 and a frequency jump of 200 kHz, the poles can be numerically calculated to be

Naming the poles of the closed-loop transfer function pi and the partial fractions of the closed loop gain Ai, the function can be transposed into the time domain yielding the transient response of the PLL for a stable system

with

A graphical representation is obtained by repeated computation of the function's numerical value over a large number of sufficiently small time steps. Finally the lock time can be read from this graph. It is defined as the time span from the beginning of the lock process up to the moment where the function's value exceeds a predefined maximum phase/frequency error for the last time. A more detailed description of the theory and some examples are published in Banerjee.4

Simulation Results
The following simulation of the lock time of a fourth-order PLL has been made with the commercial mathematic tool MathCad 8 Professional.5 This is a self-documenting algebraic and numerical tool and an industry standard for technical calculations. The input to the MathCad program used is shown in Appendix A .

In the first step of simulating the lock time the user defines the properties of the phase-locked loop: VCO gain factor, phase detector gain factor, loop filter component values, and start and stop frequencies. Second, the nth order polynomial method or the PT2 approximation method is applied to the closed-loop transfer function. The last step is a numerical pole analysis. A typical result of such a simulation is shown in Figure 4 .


Fig. 4 Mathcad simulation results.

How to Measure Lock Time

Spectrum Analyzer Method
A spectrum analyzer with frequency demodulation capability can be used to do lock time measurements based on the previous theoretical considerations. The following step-by-step procedure is based on Application Note 1EF08-1E.6

(a) Set the frequency demodulation option on the analyzer and choose the appropriate demodulation bandwidth. It has to be larger than twice the frequency step to be performed by the PLL under test.

(b) Choose the bandwidth of the post-detection (audio frequency, AF) low pass filter on the analyzer.

(c) Set the pre/post trigger and sweep times on the analyzer so that the PLL lock process is visible in its total length or at least in the time interval where the remaining frequency error meets the lock criterion for the first time.

(d) Set the frequency resolution of the analyzer so that the actual frequency deviation can easily be checked versus the lock criterion.

(e) Set the center frequency of the analyzer to the end frequency of the PLL.

(f) Connect the output of the PLL to the input of the analyzer while being careful not to overload the input. A signal attenuator (built into the analyzer or external) may be necessary. Set the reference level of the analyzer according to the signal level at the instrument's input.

(g) Use the spectrum analyzer in external trigger mode. The trigger signal can be derived from the programming data of the PLL under test (the 'Data valid'/'Enable' pulse may be used).

(h) Program the PLL to the start frequency and wait until it has settled. Connect the trigger line to the analyzer or arm the trigger input.

(i) Program the PLL to the stop frequency.

(j) Take the reading of the measurement (time span between the trigger event including pre/post trigger delay and the moment where the remaining frequency deviation becomes smaller than the allowable error).

Some restrictions and trade-offs must be considered when setting the different operating characteristics of the spectrum analyzer. The demodulator has an inherent settling time. This must be sufficiently small compared to the lock time of the PLL. A larger demodulation bandwidth reduces the settling time. However, increasing the bandwidth results in larger residual frequency modulation (residual FM) on the analyzer, which in turn reduces the useful frequency resolution.

At a given demodulation bandwidth the residual FM can be reduced by choosing a smaller bandwidth for the post-detection low pass filter. However, this increases the demodulator settling time.

The spectrum analyzer may offer two options for frequency demodulation: real-time and offline. In the latter mode the analog event (settling of the PLL under test) is sampled and the extracted signal characteristics are stored in a digital memory. As this has a finite capacity only, a limited number of samples can be taken - the product, demodulation bandwidth times sweep time, has an upper value depending on the measuring instrument's hardware.

If a spectrum analyzer with frequency demodulation capability is not available but a modulation analyzer is, the measurement can be done in a similar way. However, an additional (digital) oscilloscope is needed to visualize the result.7 This method will not be described here.


Fig. 5 Lock time measurement systems.

Mixer Method
The mixer method's measurement setup is shown in Figure 5 . The system consists of a PLL under test, a reference signal generator with a tunable phase offset, a passive mixer that works as a phase detector, an isolator and an amplifier to scale the signal level of the PLL output, an oscilloscope for measuring the output of the mixer and a computer to program the PLLs operating parameters and to trigger the oscilloscope.

The mixer and spectrum analyzer methods are not only different with regards to the hardware requirements but as the mixer acts as a phase detector, the theoretical background for error frequencies set out above in the Lock Time Calculation section must be adapted.

The following step-by-step instructions show how to perform a lock time measurement.

(a) Program the PLL to a frequency RF(t) in the desired operating band.

(b) Tune the generator to an output frequency LO(t) different from RF(t).

(c) Observe the signal IF(t) (mixer output) in continuous trigger mode on the oscilloscope - it should be a sine wave. Adjust the vertical offset of the oscilloscope display so that the mean DC level of the mixer output lies on the 0V-level of the display. Read the amplitude value A of the sine wave.

(d) Tune the generator to an output frequency LO(t) = RF(t).

(e) Observe the signal IF(t) in continuous trigger mode on the oscilloscope - it should be a DC signal. If it is located on the 0V-level of the oscilloscope display, everything is fine. If not, tune the phase offset between the generator reference frequency output (also the reference frequency of the PLL) and the high frequency output (the LO(t) signal) until this display condition is met.

(f) Switch the oscilloscope to single trigger mode. The programming bus 'Data valid'/'Enable' signal is the trigger event input.

(g) Tune the generator to the output frequency LO(t) different from RF(t). The lock time of the PLL for a frequency jump RF(t) ® LO(t) will be measured.

(h) Program the PLL to the frequency RF(t) = LO(t). The oscilloscope should display the characteristic curve of the lock process.

(i) Determine the lock time.

The lock time is measured as the time interval from the programming event step (h) until the displayed oscillation crosses for the last time the limits of the 'error band.' The band is symmetric to the 0V-level and its level limits are related to the allowed remaining angle offset when the PLL is considered to be locked.

Let a be the 'error angle,' that is, the small angle which remains to be compensated through PLL regulating action after locking is formally considered to be finished, then the outer level limits of the 'error band' are calculated as follows: |error| = |A sina|. A stands for the measured amplitude of the mixer output signal if RF(t) is different from LO(t).


Fig. 6 Mathcad simulation and visualization the lock criterion in the mixer method.

Figure 6 displays the procedure by means of a MathCad simulation of Equation 11. Note that the amplitude axis represents phase offsets since the mixer acts as a phase detector. However, phase and angular frequency are related as indicated in Equation 10.

IF(t) identifies the mixer output signal (a phase), A the amplitude of this signal, Dw(t) the time dependent frequency error and f0 the initial phase error which is compensated in the measurement procedure. The exact expression of Equation 10 would also have a term in 2w (twice the input frequency), but it is assumed that this high frequency is filtered out by the measurement setup. Integrating Equation 7a as shown in Equation 10 gives

with

A term fe ≠ 0 means that theoretically the PLL does not need an integer number of oscillation periods to completely eliminate the frequency offset between the two mixer inputs. In PLLs with phase-frequency detectors this remaining fe ≠ 0 is at last reduced to zero in a phase lock process.

The MathCad simulation results imply that f0 in Equation 11 has taken the value

This reproduces the fact that a PLL does not only compensate frequency but also phase errors and that the initial conditions in the measurement (f0 ) are set in a manner that the mixer output is zero at the end of the lock process.

With this preset

A similar reasoning using Equations 7b and 8b yields

where

a = small error angle expressed in radians, which allows the use of the equivalence sin a &ap; a

and finally the lock time tL (calculated for a specified error angle) is

An oscilloscope snapshot from a lock process is shown in Figure 7 . The frequency step is 75 MHz with a third-order loop filter configuration, widely used in GSM900 MHz systems. The relatively big frequency step simulates the lock behavior in duplex operation.


Fig. 7 Lock process snapshot.

Comparing Numerical and Measurement Results

Appendix B shows some lock time measurements (mixer method) versus PT2 and polynomial calculations for a given integer PLL with a standard GSM third-order loop filter. Besides the magnitude of the frequency jump, the filter component values were modified in the successive rows of the table.

Since the system is of fourth-order, it could be expected that the calculations using the nth order polynomial method would resemble much more the actual measurements than the PT2 results. Looking at the table, one realizes that this obviously is not the case. Moreover, measurements and corresponding calculations do not differ much; there is an average relative error of approximately ten percent. However, fluctuations in error magnitudes are rather large (from 2 to 17 percent). They are caused by numerical errors, tolerances of actual components with regard to their nominal values, and limited accuracy and reproduceability of measurements.


Fig. 8 Second-order loop filter.

To get an idea of the behavior of a second-order loop filter (third-order system - see Figure 8 ), a comparison between the measured and calculated lock times in a Bluetooth8 application are shown in Appendix C . The VCO and phase detector gain as well as the component values of the loop filter were altered for the different measurements, performed with the spectrum analyzer method.

As inTable 1 the measured and calculated values of the lock time do not, in general, differ very much: there is an average relative error of approximately 10 percent. Furthermore, there is no big difference in the errors of N-pole and PT2 calculations. Thus, the easier-to-use PT2 method is sufficient in standard applications.

To summarize, it can be said that lock time calculations yield a very good starting point for further optimizations of the hardware PLL. However, the tables also show that, sporadically, measurement and calculation offsets may be very significant. This means that circuit parameter fine tuning in accordance with measurements of the actual PLL performance is needed at least for more demanding systems in order to account for the actual component parameters (charge-pump currents, loop filter resistor and capacitor values, VCO gain) and parasitics, especially since some of the parameters (currents, VCO gain) may depend to some extent on the precise operating point of the corresponding PLL function block.

Some Practical Hints

Lock time can be shortened by increasing the charge-pump current, VCO gain and cut-off frequency of the low pass loop filter. However, the stability of the loop (phase margin) must not be impeded and more bandwidth means more phase noise and spurious. The latter can be reduced to some extent through the use of a higher order filter, but designs beyond third-order are rather impractical and of little additional benefit.

These limits can be overcome with fractional-N PLLs, mostly of third- and possibly higher order SD type (here the order characterizes the SD function block, not the complete system). They are very complex and only feasable as highly integrated circuits. However, the fundamental building blocks of the PLL remain the same as shown originally. Only the divide by N is replaced by a multi-modulus divider whose mean factor is N. Taking this value as a basis for calculations, determination of fractional-N PLL lock times should be possible as described in this article.

Conclusion

This article has gone through a rigorous derivation of the equations involved in predicting lock time and the transient response of synthesizer PLLs. A second-order and a fourth-order model are presented. The second-order model is an accurate and easy to use method to analyze the lock time. The fourth-order analysis uses no mathematical approximations other than the continuous-time approximation for the phase detector. Based on actual lock time measurements it was demonstrated that even the simplest second-order method assuming a linear PLL behavior can yield very good results.

References
1. Application Note AN535, Phase-locked Loop Design Fundamentals , Garth Nash, Motorola Semiconductor.
2. F. Gardner, Charge-Pump Phase-Lock Loops, IEEE COM-28, No. 11, 1980.
3. D.H. Wolaver, Phase-locked loop Circuit Design , Prentice Hall.
4. Dean Banerjee, PLL Performance, Simulation and Design , National Semiconductor, Second Edition, 2001.
5. http://www.mathcad.com.
6. Application Note 1MA15-0E, Measuring Frequency Settling Time for Synthesizers and Transmitters , Herbert Schmitt/Roland Minihold, Rohde & Schwarz.
7. Application Note 1EF08-1E, Transient Measurements on GSM/PCN Synthesizers , R. Minihold, Rohde & Schwarz.
8. http://www.bluetooth.com.

Florian Krug received his Dipl. Ing. degree in radio frequency engineering from the Technische Universitaet Muenchen, Germany, in 2001. Since then, he has been working toward his Dr. Ing. degree at the Institute of High Frequency Engineering at the Technische Universitaet Muenchen. His current research is focused on analysis of electromagnetic compatibility problems using modern spectral estimation methods and classical frequency domain measurements. He is a student member of IEEE, IEE and VDE.

Jean Wilwert received his MS degree in electrical engineering from the University of Karlsruhe, Germany, in 1985, then joined Siemens Semiconductor Group, which became Infineon Technologies in 1999. He has designed high speed digital integrated circuits in both bipolar and BiCMOS technologies for telecom and networking applications, as well as RF circuits for wireless communication (digital cellular and cordless, Bluetooth) with emphasis on phase-locked loops.

Appendix A : Mathcad Input Data

APPENDIX B

Measurement and Simulation Results for a GSM PLL

Frequency
Jump
(MHz)

Lock Time
Measurement
(
ms)

Four-pole
Simulation
(
ms)

Two-pole
Simulation
(
ms)

Four-pole
Absolute
Error (
ms)

Two-pole
Absolute
Error (
ms)

Four-pole
Relative
Error (%)

Two-pole
Relative
Error (%)

0.2

270

240

275

30

5

11

2

75

474

435

432

39

42

8

10

75

476

437

446

39

30

8

7

75

530

445

470

85

60

16

13

75

532

442

458

90

74

17

16

 

APPENDIX C

Measurement and Simulation Results for a Bluetooth PLL

Frequency
Jump
(MHz)

Lock Time
Measurement
(
ms)

Three-pole
Simulation
(
ms)

Two-pole
Simulation
(
ms)

Three-pole
Absolute
Error (
ms)

Two-pole
Absolute
Error (
ms)

Three-pole
Relative
Error (%)

Two-pole
Relative
Error (%)

100

112

100

118

12

6

11

5

100

110

90

118

20

8

18

7

100

112

120

115

8

3

7

3

100

164

120

115

44

49

27

43

100

91

90

95

1

4

1

4

100

100

85

95

15

5

15

5

100

86

95

118

9

32

10

27

100

136

99

120

37

16

27

13

100

112

105

120

7

8

6

7

100

112

100

115

12

3

11

3

100

121

125

140

4

19

3

14

100

110

128

140

18

30

16

21

100

117

105

120

12

3

10

3

100

110

100

115

10

5

9

4

100

119

125

130

6

11

5

8

 

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