# PLL Synthesizers: A Switching Speed Tutorial

#### Overview of switching speed as it relates to the design of phase locked loop synthesizers

*Tutorial*

*PLL Synthesizers: A Switching Speed Tutorial *

*Bar-Giora Goldberg Peregrine Semiconductor Corp. San Diego, CA*

The phase noise and noise floor of signals is a fundamental property and a constant challenge in the design of radio and wireless networks. Traditionally, phase noise has been the main concern of phase locked loop (PLL) designers.

Recently, switching speed has become a critical parameter in the design of PLL synthesizers, especially for modern wireless networks such as 3G, WCDMA, WLANs and Bluetooth technology. When frequency hopping, the time to settle is "dead time." The difficulty is compounded since better speed cannot be obtained at the cost of compromising the spectral purity. High resolution, fast hopping, economical (size, cost, power), single loop and integrated single chip synthesizers are but a recent possibility. Only the combination of on-chip RF, digital, analog and digital signal processing (DSP) technologies can offer this advantage, for networking as well as for spread spectrum (frequency hopping), anti-multipath/fading technology.

Speed and speed-up are standing challenges in modern wireless networks, without established and well known effective solutions. The purpose of this article is to briefly review switching speed theory, mechanisms, speed-up and computer aided design (CAD) to demonstrate simulation tools and explain the various options and methods available to the designer, as well as focusing on some of the challenging technical issues and design trade-offs.

**PLL Fundamentals**

The reader's familiarity with PLL theory is assumed. However, a short summary of fundamentals and terminology follows:

A second-order PLL serves as the basis for all PLL synthesizer design.

The main second-order transfer function is given by

where

s = complex Laplace transform

N = total division ratio

x = damping factor

w_{n} = loop natural frequency

Most PLL designers, especially for synthesizers where third- and fourth-order loops are common, use a different terminology, and deal mainly with the open loop gain and phase.

For a loop filter with a VCO voltage sensitivity constant (Kv), a phase-frequency detector (PFD) and a voltage-current converter or charge pump (CP) with a constant (Kp), and a passive loop filter, as shown in ** Figure 1 ** , and a division ratio N, the open loop gain is given by

For a second-order loop, the open loop transfer function is given by

where

T1 = R1C2

For a third-order loop, it is

where

Typical third-order open loop gain and phase plots are shown in ** Figure 2 ** , where m is the frequency offset.

The important characteristics to note are:

- The open loop gain decreases monotonically.
- The decrease rate close to the origin is -12/dB per octave (two poles in the origin).
- At some point (a function of loop bandwidth), the decrease rate changes to -6 dB per octave. This change in slope occurs because the zero in the transfer function (1+sT1) starts to be "active" and compensates for one of the poles in the origin.
- The open loop gain |OL| is 1 when the slope is -6 dB per octave (stability condition). The frequency at which |OL| = 1 is called wp, wp = 2pfp. Generally, wp = 2xwn, and for synthesizers, wp ~ 2wn. In this article, the loop bandwidth is referred to as wp.
- At wp, the phase margin is at least 35° away from 180°, and most designers require a minimum of 40° to 45° (stability conditions). An optimal design will maximize the phase margin at wp.

The switching speed is defined by the time Tsw it takes the PLL to hop from its stable state Fo, by a certain frequency excursion, dF, and converge to the new frequency Fo ±dF.

Since the process is that of asymptotic convergence, a tolerance, df must be defined. This is usually done by defining the frequency error of convergence (for example, 1 kHz or 0.1 ppm) or sometimes by defining the phase error from complete settling (0.1 radian is an industry standard).

**Fundamental Switching Speed Equations**

There are actually two fundamental equations related to switching speed that cover the majority of the issues. The time solution of the second-order differential equation can be approximated as follows: If the loop hops dF (Hz), then an approximate equation for the frequency error (from final frequency) is given by

df(t) , dFe-xwnt (5)

Therefore, to meet a specific settling error df, the time Tsw it takes to achieve it is given by

For example, the time to hop dF = 25 MHz, and settle to within df = 1 kHz, with wp = 20 krad/sec (loop bandwidth of approximately wp/2p = 3.17 kHz) will last approximately Tsw = 2ln(25000)/20000 , 1 ms. Note that the speed is inversely linear with wp (or wn) but logarithmic with dF or df. A change of 10 to 1 in dF (or df) is equivalent to a change of 2.3 in wp. Better speed obviously requires an increased loop bandwidth. The second fundamental equation, also an approximation, is given by

The proof is quite simple. The second-order open loop gain is given by

Now, wp is within the response range where the slope changes from -12 to -6 dB/octave; therefore, it is clear that the zero in the numerator is active. The open loop gain can be approximated, with s = jwp, as

therefore

In summary, the speed is proportional to the loop bandwidth; the switching speed depends on the parameters dF, df, Kv, Kd, R1 and N. These are the parameters that will be used in determining (and manipulating) the speed and speed-up techniques.

**Switching Speed Simulation**

The switching speed in a PLL requires a complex analysis. Specifically, in transition, the PFD is not linear, hence the switching transient is subject to a nonlinear behavior that complicates the analysis.

The nonlinear analysis is done mainly in the time domain, using SPICE modeling. However, good insight can be gained by the much abbreviated frequency domain analysis, using the inverse Laplace transform.

When this is applied, the system is assumed to be linear. The use of the simulator to check this assumption is easily done, as will be shown later.

In a PLL system, the phase of the reference frequency (Fr) and the feedback signal (Fvco/N) are compared. The loop is in steady state only when both the phase and frequency of these two signals are equal. However, note that the only element that can change both phase and frequency is the VCO. Moreover, in order to change phase, the VCO must change frequency, since f = "w(t)dt, and the control voltage changes w and not directly f. Therefore, a typical frequency transient will usually have an overshoot (or undershoot), as shown in ** Figure 3 ** .

The ideal frequency change (smooth phase transition) shown in ** Figure 4 ** will suffer a transient. The goal is to minimize this transient.

When the loop is locked, the phase error between the reference Fr and the feedback signal Fvco/N is practically zero. A typical PFD has a linear characteristic only when the phase error is less than 2p, as shown in ** Figure 5 ** .

The real characteristic of the PFD is actually that of a sampled error, sampling at Fr. In the locked state, the sample time is in the 3 to 10 ns range (the output spikes from the CP cause spurious frequencies at Fr and its harmonics); however, during the transient, the phase error shows as the duty cycle of the error, approximately at the Fr rate, until settling.

When commanded to a new frequency, the feedback divider N changes value and a phase error starts to develop immediately. The initial phase gradient is easy to calculate, given approximately by 2pdFt/N. At the same time, the loop starts to correct this error. The behavior of these two opposing forces depends on the loop dynamics since eventually the loop will settle to the locked state again.

**Speed Simulation**

The following analysis is a simulation of a third-order loop, using the inverse Laplace transform, for a 2400 MHz loop, having Fr = 200 kHz. N ~12000, Kv ~ 67 MHz/V and Kp = 1mA/2p and fp ~ 20 kHz.

The close loop response CL(f) is shown in ** Figure 6 ** . The frequency error Y(t) for a 25 MHz switching speed transient is shown in

**. Settling to within 1 kHz lasts approximately 160 ms, for a frequency hop of 25 MHz.**

*Figure 7*The instantaneous phase error can also be checked (if it exceeds 2p, the linearity is violated). Remembering that f(t) = (2p/N)"f(t)dt, the phase error is shown in ** Figure 8 ** .

Apparently, in this case, the phase error developing at the PFD output is very small. The linearity assumption of the loop analysis is justified and does not require modifications. This, of course, is not always the case.

Remember that the divider has a very high value and the loop has a wide bandwidth. The maximum frequency error (at the phase detector) is 25 MHz/12000 Hz ~ 2083 Hz, not much for a 20 kHz loop. For a frequency error of 200 Hz at the output, the frequency error at the phase detector must be 200/12000 = 0.016 Hz.

**Speed-up Options **

There are a variety of options to speed-up the loop. Observing the fundamental switching speed equations given previously, it becomes clear that the two fundamental parameters concerning speed are dF, the frequency excursion, and wp, the loop bandwidth. As a demonstration of the difficulty, assume a VCO with Kv = 20 MHz/V is used and a convergence to within 200 Hz is desired, then the voltage error allowed on the control line is in the 10 mV range.

The only way to affect dF is by pre-tuning the VCO using a look-up table. This is quite tedious and not done in large production runs, but is quite effective.

All other speed-up methods actually increase wp (or wn), (wp = KvKpR1/N). Overall, the majority of the industry implements a simple mechanism to increase loop bandwidth and loop dynamics.

Speed-up by increasing loop bandwidth mainly deals with the first part of the locking mechanism and attempts to charge the main capacitor (C2) close to the final value. This does not necessarily constitute the major part of the hop time. Also, changing the loop parameters with analog signals introduces an analog transient that can "throw" the loop away from the locked state.

The most popular speed-up technique is to increase Kp. In parallel to the regular CP, there is a secondary CP (or extra current sources), controlled by the same logic (PFD output), but with more current. Upon activation the secondary CP becomes active, thus charging (or discharging) the main capacitor C2 faster and increasing the loop bandwidth (as Equation 2 shows). In many cases, the speed-up CP is just in parallel to the normal one; in others it is available on a separate pin and can be connected directly to C2.

The effect on the close loop bandwidth, for an increase in Kp by 8 times, is shown in ** Figure 9 ** . As can be seen, the close loop transfer function becomes wider and somewhat oscillatory. This is usually corrected by reducing the value of R2. Thus, most PLL chips that have speed-up employ an extra CP plus an analog switch that enables connection of a parallel resistor to R2 for the speed-up duration, in order to stabilize the loop.

The practical procedure to optimize speed-up time is to use a look-up table controlling processor that determines the speed-up activation time, based on the size of the excursion dF.

Another way to achieve similar results is obtained by changing N. If, for example, N is reduced eight times, wp increases significantly, as Equation 8 shows. Here again, to stabilize the loop, the value of R2 must be changed. A comparison of the closed loop bandwidth and switching speed transient for two values of N and with or without R2 adjustment is shown in ** Figure 10 ** .

Obviously, if the value of N is reduced, Fr has to change accordingly to "steer" the loop to the same final frequency. This can be done by changing the reference divider accordingly, a function available in all PLL chips, such that

Fo = Fr x N = N x Fx/R

where

Fx = the crystal frequency

R = the crystal divider

Intuitively, by increasing Fr, an error generation at a much higher rate is allowed. For example, for Fr = 200 kHz, the error is generated only once every 5 ms, but when Fr is increased eight times to 1.6 MHz, an update occurs each 0.625 ms. In some ways, this is a more convenient procedure because changing the division, especially by binary numbers, involves only a right shift of the counter's contents (both main and reference). Of course, fractionality sometimes has to be included for the division to result in exact numbers. Also, it does not involve switching current sources (in and out), always a concern for transients.

The issue is complicated somewhat by the fact that just increasing the loop bandwidth does not necessarily or significantly improve speed. The design requires optimized parameters and significant CAD design work.

An alternative solution, mentioned previously, is the option to reduce dF by pre-tuning the VCO. This is not often used.

If the VCO can be pre-tuned to the approximate frequency then the control voltage from the CP hardly changes (another advantage is that usually the noise performance depends on the DC operating point of the CP), dF decreases and the loop must perform only the final lock.

The procedure is to add a look-up table followed by a digital-to-analog converter (DAC) whose output voltage can be added to the control voltage. After the initial DAC hop, the PLL performs the final lock.

There are two fundamental issues here: How is the VCO accurately pre-tuned, especially in large production runs (the VCO has a significant control voltage tolerance) and what is the noise contribution of the DAC?

As an example, assume an 8-bit DAC is used. The range will be divided into 256 sections, each covering 25 MHz/256, approximately 100 kHz. Therefore, the overall uncertainty goes from 25 MHz to approximately 100 kHz. This is significant, and if the process can be optimized, it can be very efficient.

How can the VCO tolerance be dealt with? Rather than being pre-tuned by a fix ROM (look-up table), a simple adaptive mechanism can be designed. On power up, the synthesizer scans 256 frequencies and stores their DC value in memory (with an A/D converter) or a non-volatile memory. More comprehensive methods are also possible as the addition of logic in chips comes almost at no cost. A qualitative comparison of switching speed as a function of dF for fp = 10 kHz is shown in ** Figure 11 ** . Other options are:

- Reduce the spurious levels (by designing a better balanced CP) and make the loop bandwidth wider. Generally, Fr spurious prevent the loop from being wider by more than Fr/25, (with spur reduction, it is possible to go to approximately Fr/10). However, the implementation is difficult.
- Use fractional designs. Fractional spurs are usually 20 to 25 dB below Fr, so the loop bandwidth can be wider.
- Use frequency lock loop techniques for speed-up.

A speed-up simulation, using the inverse Laplace transition, is shown in ** Figure 12 ** . Note the change in slope after 15 ms.

When calculating or simulating speed, Ohm's law should not be forgotten. If the power supply is 3 V and the CP current is 1 mA, the resistor R1 value cannot be too high, otherwise too much voltage develops and affects the capacitor C2 charge time.

**Conclusion and Challenges**

The switching speed is emerging as a challenging requirement for single loop, single chip PLL designs. Speed is mainly a function of loop bandwidth, but in many cases the loop bandwidth cannot be too wide because of phase noise considerations. Speed-up techniques have been devised to improve PLL transient time, but most of them have limited efficiency.

One solution the industry will probably adopt in the future is the use of complex Sigma Delta fractional PLL architectures,3 which allow a high reference frequency and wide loop bandwidth, while maintaining resolution and a good phase noise profile (low division). This technique is already being implemented.

In addition, speed-up techniques will have to be improved. For the WCDMA and 3G markets (and others that are emerging) a reasonable goal is 100 to 150 ms for a dF = 60 MHz excursion and a convergence to df = 250 Hz.

**References**

1. B.G. Goldberg,* Digital Frequency Synthesis Demystified* , LLH Publishing, 1999.

2. Robert Adler, "A Study of Locking Phenomena in Oscillators," *Proceedings of the IEEE* , October 1973, pp. 1380-1385.

3. B. Miller and B. Conley, "A Multiple Modulator Fractional Divider," *IEEE 44th Annual Symposium on Frequency Control* , 1990.

4. Roland Best, *Phase Lock Loops* , McGraw-Hill, New York, 1984.

*Bar-Giora Goldberg is advanced architectures director at Peregrine Semiconductor Corp. in San Diego, CA. The company designs and manufactures wireless and photonics components and super-components products using an Ultra Thin Silicon process on sapphire substrate. Mr. Goldberg can be reached via e-mail at ggoldberg@peregrine-semi.com. *