- Buyers Guide
5G and IoT Supplement
Ultraminiature VCOs for Wireless Applications
San Diego, CA
Many electronics manufacturers in the subscriber industry have realized tremendous reductions in semiconductor and passive packaged products since the advent of surface-mount assembly equipment in the mid-1980s. This has been evidenced of late with the introduction of chip scale packages (CSP) and ball grid arrays (BGA), especially in the area of semiconductor products. While CSPs and BGAs are relatively new, other die-approximating package solutions have been in existence for years, including flip-chip packages and the traditional die attach via bond wire. However, the CSP is unique in the sense that it is targeted for high volume, dense integration onto printed circuit boards without additional post processing (for example, the application of underfill). Furthermore, various companies are now applying CSPs to passive technology by way of resistor arrays and ladder filter networks, again to address the problem of dense packaging and integration onto PCBs. The latest member of the package reduction movement has been discrete passives, such as resistors, capacitors and inductors. While thin film capacitors and resistors have been prevalent in the use of military electronics due to their size and performance, the costs were prohibitive to realize their use in a consumer end product such as a wireless local area network (WLAN) card, cellular phone or hand-held Internet terminal. However, technological process improvements have now positioned low cost, very small size passive components at the forefront of subscriber technology to meet the ever-growing demand for smaller, lighter personal communicator products.
THE USSP VCO SOLUTION
Recently, the aforementioned technologies have been combined to develop a densely integrated, compact VCO platform called the ultra small-scale package (USSP) family of VCOs by working with leading subscriber manufacturers. The USSP family incorporates the advantages of extremely small 0201-sized components coupled with CSP-packaged silicon bipolar transistors and silicon hyperabrupt varactor diodes to deliver exceptional performance in a compact, surface-mount package measuring 0.2" × 0.2" × 0.06" (5 × 5 × 1.5 mm). This product line realizes tremendous cost savings over existing technology by utilizing low cost proprietary thin-film technologies to deliver not only a high performance solution in a small form factor, but also a solution uniquely geared towards satisfying demanding cost-sensitive end consumer applications such as WLAN cards, 3G phones and wireless personal digital assistants.
The use of proprietary chemical vapor deposition processes with high (5) to very high (> 12) dielectric constant substrates allows the company to offer a highly integrated substrate in a small form factor. Inductors and resistors are then sputtered on top of successive layers over the circuit traces leaving only a handful of 0201 components to be placed through high speed, precision optic robotics. These remaining 0201 components require physical placement because they cannot be realized due to physical planar area constraints. The only other components to be automatically placed involve the active devices. The advantage of this type of process becomes quite evident in the area of board space; instead of building out, multiple layers of components and their respective interconnects are now built up. Since the added geometry of the resistors and inductors are quite small to begin with, the additional height incurred is negligible (usually on the order of angstroms).
The remainder of the assembly process involves the use of some leading-edge surface-mount placement equipment. By working closely with leaders in very high speed, precision optics-based surface-mount assembly equipment, the automated assembly process has been optimized with 0201 components. This investment has also poised the company to realize component placement accuracy with 0107 components for the upcoming CSP solutions for silicon bipolar transistors. From this technology base, sputtered capacitors will be incorporated for further component count reduction and potential future reduction in packaging.
Once the assembly process is complete, the substrates are then convection oven reflowed, singulated, trimmed, tested and packaged in conventional tape-and-reel format for integration into the subscriber unit. The advantage of this entire process is that existing processes can be used and no additional process steps are introduced that can potentially add cost to the end product.
A USSP EXAMPLE
The USSP2330L VCO reflects the culmination of the described technologies. Figure 1 shows the mechanical dimensions of the product. It becomes quite clear this small solution was developed for subscriber terminals for 802.11b WLAN cards. While developing this compact VCO some key electrical points were also considered. As a result, few performance features were compromised for the sake of package reduction.
The operating bias was required to be less than 3 VDC to minimize the presence of additional voltage rails, subsequent cost and additional PCB space. Furthermore, the design had to minimize current consumption since the end application depends on battery power while delivering modest output power. The design and implementation of the tuning inductors through the chemical vapor deposition process along with the choice of low current, active devices presents a solution that was capable of operating from a 2.7 VDC bias while drawing only 8 mA. With this biasing, the device was characterized over the entire operating temperature range from 40 to +85°C and generates 0 dBm nominal output power. In addition, the device is capable of tuning the desired range of 2300 to 2360 MHz within 0.5 to 2.5 V DC of control voltage to support existing charge pump outputs from off-the-shelf phase-locked loop manufacturers. The VCO's typical tuning curve over temperature is shown in Figure 2.
Another concern was in the area of phase noise performance. The tendency of oscillators is to degrade in phase noise performance with a reduction in size. This degradation is natural considering the reduction in cavity size, which leads to a subsequent increase in parasitic noise. A few techniques can be employed to offset this degradation. Some of the more popular approaches include utilization of high dielectric constant substrates, high fT bipolar transistors, utilization of noise cancellation/minimization techniques and, in general, to arrange the circuit topology to minimize the effect of parasitics. Unfortunately, the implementation of noise cancellation/minimization techniques have a practical constraint imposed by the key design goal of package reduction. Common implementations of noise cancellation techniques return an out-of-phase signal back to the oscillator's tank circuit; in most cases, additional AM noise can be reduced, but at the expense of additional components. As mentioned, this is not a viable option considering the space constraints of a 0.2" × 0.2" area for real estate.
However, by working closely with leading bipolar and substrate manufacturers, three of the four approaches mentioned were incorporated to realize a design that offers exceptional phase noise performance. The result of the oscillator's single side band (SSB) phase noise performance is shown in Figure 3. By realizing a typical SSB phase noise of 85 dBc/Hz at 10 kHz from the carrier, plans to conduct further research to determine how to improve this performance while driving the frequency of operation even higher are underway. Currently, laboratory development seeks to provide products for the 1800 to 1900 MHz regions with a SSB phase noise figure of 95 dBc/Hz at 10 kHz. Most of this effort is directed at higher dielectric constant substrates that are fabricated using low cost production techniques. The company is currently engaged with leading subscriber manufacturers to realize this goal for 3G subscriber production in the near future.
Through the use of the CSP/0107 package and ultra small 0201 passive component package technologies, proprietary thin-film technology, utilization of advanced surface-mount assembly equipment and proprietary voltage-controlled oscillator technology, a revolutionary and ultra small VCO solution has been introduced to the wireless market. The USSP family of VCOs optimizes key VCO parameters, including frequency tuning, control voltage, power consumption and SSB phase noise performance in a compact surface-mount solution measuring just 0.2" × 0.2" × 0.06" (5 × 5 × 1.6 mm). Further areas of packaging reduction and performance enhancement are continuing to be explored for future development. For now, prototype delivery has begun with applications being targeted at WLAN cards and next generation cellular subscriber products. Production delivery is expected by the end of the third quarter to support 3G phone development. Further questions regarding custom development can be addressed to the USSP Application Engineering Group via email to firstname.lastname@example.org.
San Diego, CA (858) 621-2700.
Circle No. 300
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