To continue showcasing the growth of the SOI ecosystem and the application drivers for ultra-low-power IC solutions, the SOI Industry Consortium has organized one day of information-sharing and networking event on April 26 and a second day targeted at RF and analog design engineers on April 27 in Silicon Valley.Activities begin at the Hyatt Regency Hotel in Santa Clara, Calif., with a full-day symposium–free to pre-registered attendees–to promote communication and establish connections among members of the growing SOI ecosystem. The following day, a training tutorial on designing ICs with fully depleted SOI (FD-SOI) technology focused on RF/mixed signal/mmWave will be conducted at the Crowne Plaza Hotel in nearby Milpitas, Calif.

The need for microelectronics that run on low power without sacrificing speed is generating increasing interest in SOI technologies. Fabless semiconductor designers, foundries and suppliers of manufacturing equipment and materials are expected to attend this year’s third annual gathering to learn and discuss how to use SOI in emerging applications with a special focus on FD-SOI and its application drivers.

The program kicks off on April 26 with two keynote addresses by Frankwell Jyh-Ming Lin, CEO of Andes Technology, and Ron Martino, vice president and general manager of NXP Semiconductors.

A session on “Products and Opportunities” will follow, featuring presentations by Andre Blum of Audi, Olivier Notebaert of Airbus, Kenichi Nakano of Sony and a speaker from STMicroelectronics.

A second session on “The Evolving SOI Ecosystem” will include talks by Dan Hutcheson, CEO of VLSIresearch; Gregg Bartlett, senior vice president of GLOBALFOUNDRIES; Jeffrey Wang, CEO of Simgui; and an executive from Samsung’s foundry business.

“Innovative Applications” will be addressed in a session featuring speakers from innovative startups including Ramkumar Subramanian, senior vice president of Ineda Systems; Loic Lietar, CEO of Greenwaves; Jens Benndorf, CEO of Dream Chip Technologies; Jean-Pascal Bost, CEO of eVaderis; and William Coven, CEO of Reduced Energy Microsystems.

The day will conclude with a panel discussion focusing on “The Needs for Ultra-Low-Power Electronics and Their Application Drivers” with panelists Wayne Dai, CEO of Verisilicon; Kelvin Low, vice president of ARM; Timothy Saxe, CTO of QuickLogic; Mahesh Tirupattur, executive vice president of Analog Bits; and Dave Eggleston, vice president of GLOBALFOUNDRIES.

Additionally, on April 27, a training day on FD-SOI design techniques will be held at the Crowne Plaza Hotel. Organized by Andreia Cathelin of STMicroelectronics, the full-day tutorial will feature world-renowned professors and industry experts delivering a series of four training sessions dedicated to energy-efficient and low-voltage design techniques for analog, RF, mmWave and mixed-signal design.

Attendees will learn about design techniques that take full advantage of the unique features of FD-SOI, including body-biasing capabilities that further enhance FD-SOI’s excellent analog/RF performance. Participants will receive concrete design examples that illustrate new implementation techniques enabled by FD-SOI technologies at the 28 and 22 nm nodes and beyond. Topics will cover basic building blocks through SoC applications.

Program details and paid registration are posted at https://soiconsortium.eu/events/27-april-2018-fd-soi-training-day/.