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An Object-Oriented Circuit Simulator

The basic software architectural guidelines of the APLAC circuit simulator program and its use of the fundamental volatage controlled current source element

July 1, 2000
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The basic ideas behind the circuit simulator and design tool APLAC are presented in this article. The chosen way of implementation of this circuit simulator is based initially on nodal formulation and gyrator transforms, leading to a very general and powerful architecture. New models and analysis functionality can be implemented in a straightforward and practical manner into the simulator built on this foundation.


Aplac Solutions Corp.

Espoo, Finland


Helsinki University of Technology

Helsinki, Finland

The APLAC simulator has been under constant development at the Helsinki University of Technology (HUT) since 1972.1,2,3 Today, APLAC is developed in co-operation with APLAC Solutions Corp. (established 1998), HUT and Nokia Corp. Since the beginning, the main (and admittedly, rather abstract) requirement of the software development has been to give the user the freedom to solve design problems without the restrictions of "the conventional simulator." In practice, this means that the smallest non-trivial common denominator of any circuit analysis task is sought, and based on that, all models and analysis methods are built. Note that this activity is in direct analogy with the object-oriented software engineering regime where specialized objects can inherit characteristics of more general ones.


Circuit simulations are simulated measurements of devices under study. By means of a computer program, the user mimics the physical operation of an electrical device and then takes virtual measurements. The measurements are typically carried out by plotting the obtained simulated data on graphs on the computer screen. Of course, basic motivation for this activity is that the alteration of the circuit is a great deal faster inside the memory of a computer than changing the real prototype. Simulations may also be cascaded to optimize the circuit to find the most suitable values for some parameters, or to find statistical properties of the design (for example, yield analysis).

From these simple guidelines it is easy to point out the most general requirements for the software of a circuit simulator. First, the simulator must contain the models for the used components. This means that the electrical behavior (typically, voltage/current behavior) of a resistor, capacitor, diode and transistor must be described for the simulator in one form or another.

Next, the components must, in general, function with as many analysis (that is, simulated measurement) methods as possible. Typically, it is of interest to study the behavior of the device both in the frequency and time domains. Even more complex cases present themselves if the device models exhibit nonlinearity. If possible, all components should be made operable in all analysis methods to avoid complex consistency issues. (Consider, for instance, an imaginary case where an inductor component would not be available in, say, transient analysis. Since the inductor is a rather basic component used, for example, to model parasitic coupling elements of microprocessor's bond wires and terminals, time domain studies of such devices would be automatically made impossible. Furthermore, inductors would not be available to build more complex components needing a transient analysis.) In particular, the small signal model of the component must be obtainable from the large signal model so that they are physically equivalent.

Fig. 1 A simplified view of a circuit simulator.

Fig. 2 A conductance and its equivalent circuit.

Fig. 3 A capacitance and its equivalent circuit.

Finally, there must be an easy way to control the simulations to find, for example, the response of the circuit at several frequencies, the best value for a component based on some figure-of-merit or the yield of the design in case of a certain variation of component values.In short, a circuit simulator can be viewed as a collection of component models, analysis methods and ways to control the analyses, as shown in Figure 1.

Now, from a software engineering point of view, the fundamental question is: how to structure the architecture of the software so that all the points above are taken into account, and so that making changes in the program afterwards is still possible and manageable.

Fig. 4 The gyrator element.

Fig. 5 Equivalent circuit of an inductor.

Several initial points can be raised: The components models are typically equivalent circuits that mimic the operation of the component with some basic set of circuit elements. From the software development and management point of view, and also from the user perspective, it is obviously very beneficial if every component model operates in every analysis method without the need for a rewrite. This requirement is denoted with edge A in the diagram. Next, the controls of the simulator must be able to govern the analyses flexibly to allow the user to specify complex analysis tasks easily (denoted with edge B). Finally, the controls must also be able to alter the behavior of the models (for example, parameter values) to facilitate, among other things, optimization and tuning of the circuit (denoted with edge C).


There are several approaches for trying to implement circuit simulator software, the original SPICE being the most ubiquitous and well known with its source code freely available. APLAC, though superficially similar to SPICE and its derivatives, is fundamentally different in the way it was designed. APLAC is a true object-oriented simulator.

As already briefly discussed, in the architecture, a fundamental idea has been to discover a basic building block from which every other component of the simulator can be derived.4,5 This element is the voltage controlled current source (VCCS). This component is the mother of every other circuit element, (for example, resistor, diode or BJT).

To formulate the analysis problem, a nodal approach is used. This means that Kirchhoff's current law is applied at every node of the circuit except the ground node. The variables of the problem are node voltages having a ground node as a reference. Each node contributes one row to the system of equations

J = Gu


G = nodal conductance matrix

J = excitation (source) currents

u = voltage vector, voltages taken with respect to some reference (typically ground) node

However complicated the original problem may be, it can always be expressed in this simple linear form by utilizing proper equivalent circuits and solution methods for the components of the analyzed device.6

Given the problem formulation principle of the simulator, how can a VCCS act in so many roles? To illustrate this, consider the following basic cases:


As seen in Figure 2, it is evident that a conductance (inverse of a resistance) is a VCCS where the control voltage is the voltage over the element itself. The magnitude of control is the value of the conductance.


By the same token, a capacitance is a current source whose feed current depends on the magnitude of the capacitance and time derivative of the voltage change across the capacitor, as shown in Figure 3.

In general, a dynamic charge source reads q = q(u), which leads to I = dq/dt.

However, there are components that require more attention. For example, a simple inductor is a component whose feed current depends not only on the voltage across the inductor, but on the time integral of the entire history of the voltage behavior. Luckily, by using a special gyrator element, as shown in Figure 4, all inductors can be represented for the simulator as pairs of gyrators and capacitors, as shown in Figure 5.20

Port 1 is excited with a current J1 = I1 , and nodal analysis is used to acquire the formula for the input impedance as

The result shows that the capacitance connected to port two is seen at port one as an inductance, whose value is L = C.

This example shows a case where the inductance could be replaced by two controlled sources and one capacitance. The capacitance could still be replaced by a VCCS, in which case the inductor would have become three current sources. In all, with gyrators, all circuit elements can be mapped to a VCCS. As a matter of fact, the nodal equations that are arrived at with gyrators are exactly the same as those that are achieved through the use of a modified nodal approach (MNA), but the use of gyrators is the much simpler method.20,22

The placement of the VCCS as the most primitive building block and then deriving more complex elements from a combination of VCCSs indicates a hierarchical approach, which is readily implemented by using an object-oriented software discipline. In other words, the basic building block now has been found on which to build the entire simulator.


Upon discovering the basic building block candidate for the simulator, a review of how it can be fitted to conduct various analysis such as DC, transient and harmonic balance is presented.


DC analysis is the essential core of the simulator7, since all other methods (except the simple linearized AC analysis) are completely mapped to the DC analysis. If the DC analysis is viewed as a measurement, it corresponds to the simple usage of a voltage meter or ammeter.

In the simulator, the mathematical background of DC analysis is the Newton-Rhapson iteration having various variations to aid convergence. To illustrate the solution briefly, the current i through a (possibly nonlinear) element u at iteration n is

by taking into account two terms in the Taylor series. Starting from u = u0 gives the element values shown in Figure 6. Then, a resistive linear DC analysis is carried out, resulting in a new estimate for the voltage (u1 ). To aid the convergence of the scheme, several different schemes are incorporated into the simulator.

Fig. 6 Linearized iteration model.

In the normal reduction strategy, whenever a new voltage ûn+1 is found it is accepted only if the current imbalance defined by a certain norm e is reduced from the previous trial.21

Model damping aids the convergence by suppressing the sequential voltage changes during the iterations. This capability is achieved by shunting the static sources with small conductances that decrease as the iteration proceeds.

Source stepping is based on the assumption that all DC voltages and currents are zero when no independent sources are present. Hence, by multiplying all independent sources by a factor k £ 1, and then letting k approach 1 gradually, convergence is better achieved.

Fig. 7 Integration model.

In a voltage limiting scheme, the step of the voltage over one iteration is limited, again aiding convergence such that

and un+1 is the unlimited solution after the last DC iteration cycle.

In diode damping the voltage limitation is especially applied to diodes, which is a difficult component due to its strong exponential voltage/current characteristics. Due to the message passing mechanism of the simulator stemming from the object-oriented background, it is easy to create a mechanism to broadcast a command to all diodes to observe the voltage changes and to adjust the damping factor b accordingly.

Because of the object-based implementation, the simulator's analyzer knows at every iteration cycle which one of the controlled current sources is the tricky one (at least when the convergence is concerned), and which specific model is the parent of this source. This feature helps the analyzer take corrective actions.


Transient analysis describes the behavior of the circuit in the time domain, mimicking the usage of an oscilloscope. In the transient analysis, the simulation uses the Forward Euler method as its first-order method. For the second-order method, the Gear-Shichman method and the trapezoidal rule are used. For example, the trapezoidal rule gives the current i at time instant n + 1 as

This relationship leads to an integration model shown in Figure 7.

Fig. 8 Equivalent circuit of i = i (u).

The utilization of this model allows a systematic solution to the simulated device in the time domain. Of course, the efficiency of the scheme is dependent on the timestep size. To maximize Dt without sacrificing accuracy, time stepping can be made variable based on the number of resulting nonlinear iterations at each timestep, or the estimated local truncation error.21

To facilitate the analysis, the analyzer sends messages to all dynamic current sources to create the displayed equivalent circuit and to load the nodal conductance matrix and current vector. Before carrying out the solution, a message is sent to all transient sources to check their time domain behavior. If changes that are too large are detected, the timestep is reduced accordingly before any attempt is made to perform one time point analysis.

It is also possible to incorporate frequency dependent characteristics into the time domain analysis.8,9 This feature is of utmost practical importance since virtually all real devices exhibit dispersion and (at least some) frequency-dependent losses. In the simulator, the scheme is to split the circuit into linear and nonlinear parts. The nonlinear part contains all components with only a time-domain representation. The Y parameter characterization of the linear part is obtained at a set of frequencies f = 0, 1/tend …N/(2 tend ). Now by means of fast Fourier transformation (FFT) or convolution, an efficient time domain equivalent circuit of the linear part becomes available.


The goal of harmonic analysis is to calculate the steady state spectra and waveforms of a (strongly) nonlinear circuit under periodic large signal excitation.12-17 This method can be generalized to cover the case of multitone excitation where the signal frequencies can be far apart (for example, intermodulation studies). It should be noted that the transient analysis previously discussed is also a method of finding the steady-state harmonic response of a circuit - it is just very inefficient, especially when dealing with circuits that have large Q-factors.

The simulator's approach is based, again, on equivalent circuits composed of current sources only, enabling a full object based implementation. To facilitate the harmonic analysis, all waveforms are represented in terms of Fourier series coefficients. This procedure means that a periodic steady state voltage can be expressed as


w0 =

T = period

N = number of harmonics

Ua,m ,Ub,m = real numbers

a = cosine coefficients

b = sine coefficients

For a nonlinear static component i = i(u), the steady state current is given by

Assuming that u(t) in Equation 7 is known, then the coefficients of Equation 8 are found by replacing u(t) in the nonlinear characteristics i=i(u) and applying FFT.

From initial guess U0 a,m , U0 b,m sample point values for u(t) are calculated using an inverse Fourier transform. The number of sample points is (at least) 2N. Values of i(t) are calculated at the sample points. Coefficients I0 a,m and I0 b,m are calculated using a discrete Fourier transform.

Each of the coefficients I0 a,m and I0 b,m will become a nonlinear function of all the coefficients Ua,m and Ub,m . Thus, each node of the circuit may be exploded into 2N+1 nodes having voltages Ua,m and Ub,m , after which currents Ia,m and Ib,m are treated as normal nonlinear static sources. The equivalent circuit of a nonlinear element i = i(u) then becomes that shown in Figure 8.

Each of the current sources in the equivalent circuit is furthermore replaced by the equivalent circuit of the linearized iteration model thus enabling a conventional DC analysis to be performed and all the convergence aiding techniques to be used. After convergence, the exploded nodes contain the spectral components of the node voltages.

In the basic harmonic balance, the N harmonics are consecutive integer multiples of the fundamental frequency. The generalized harmonic balance12,13 or spectral balance deals with "almost periodic" waveforms: there is still a finite number of harmonics, but their frequencies are no longer in a simple relationship to each other.


Thus far, the simulator's circuit theory background has been described and how the features are implemented was presented. But how does the designer tell the simulator what to do? The analysis tasks of APLAC are governed by means of a simulation language. The circuit is described to the simulation as a netlist of element models. For example, a line of APLAC language file describing a simple resistor would read

Res R1 n1 out

+ 1K+(7/(t+20))

+ L=x1 C=3.5m


R1 = name of the resistor

n1 and n2 = nodes connected by this resistor

The second line stands for the component value. Any mathematical formula can be used in place of a component value. In this example, a simple function of time has been added to the '1k' (1 kW). On the last line are the parasitics, which are actually optional. L is the series inductance, here equal to a variable x1. C is the parallel capacitance and is equal to 3nF. From a netlist point of view, APLAC is evidently a SPICE-like simulator.

What sets the simulator apart from SPICE are the built-in programming capabilities connected with the netlist. APLAC contains simple controls for performing various analysis tasks. For example, the Sweep statement carries out a collection of successive related analyses (analyses varied as a function of frequency or time). The example becomes

Sweep "TRANsient analysis"

LOOP 501 TIM LIN 0 20/ff Y " " "V" 0 10

Display Y "n1" Vtran(n1)

+ Y "out" Vtran (out)


and creates a time sweep at 501 points from zero time to 20/ff (ff is a variable having units of hertz, defined elsewhere). The Y axis is defined to show volts on a scale of 0 to 10 V. Output is the transient voltage at nodes called n1 and out.

However, more complex controls can be built up by means of the simulator's language. For example, APLACvar is a variable definition in APLAC language. Simple assignments can naturally be performed to APLACvar, but more complex definitions are also possible. For example, the variable can be optimized. This means that whenever something, (a resistance value), is defined by an optimizable APLACvar, the value of the resistance can be automatically altered by some dedicated optimization method.18,19 Moreover, APLACvars can have statistical properties. This feature has importance especially in yield (Monte Carlo) analyses, where values are not fixed but instead statistical distributions.

The APLAC language also contains constructs for controlling the execution of the simulation. Conditional statements (If-Then-Else), For-Next-loops and other such standard constructs are available. It is also possible to perform real and complex arithmetic in scalar, vector or matrix formats. String operations are also available. Mathematical expressions are written in a program-like manner and new parametrisized functions may be defined. The simulator's language maps the lines of the input file to constructors of APLAC's objects using inverse polish notation, thus making it efficient and versatile. In the end of this chain-of-command, all components are finally mapped to VCCSs.


By now noting that the VCCS element is also available in APLAC language, it is easy to realize that the modeling possibilities of the simulator are versatile. To illustrate, a simple diode model is presented. It's definition in APLAC language reads

DefModel SimpleDiode 2 n_in n_out PARAM 4 IS N XTI EGO

Default IS=0.01p N=1.0 XTI=3.0 EGO=1.11

#define VT (N*Boltzmann*TEMP/ elemQ)

AplacVar IsT IS*(TEMP/TNOM) ^(XTI/N)*exp((EGO/VT)*((TEMP/TNOM)-1))

VCCS "own_diode" n_in n_out 1 n_in n_out

+ ( IsT*(Exp(CV(0)/VT)-1), IsT/VT*Exp(CV(0)/VT))


The model has two nodes (n_in and n_out) and four parameters that can be passed into the model (PARAM 4 IS N XTI EGO). The values can be defaulted to sensible values to avoid any unphysical situations. Frequently needed variables can be predefined with the #define statement.

It is easy to see that the equation defining the current/voltage characteristics for this diode is

The VCCS is spanned between nodes n_in and n_out, and there is one controlling voltage between the same nodes (1 n_in n_out). NONLINEAR means that simple linear assumptions can not be made with this element. DERIV means that the derivatives of the VCCS are also supplied in the VCCS definition.

Now this model is available in any analysis task simply by defining components (assuming default parameters) as

SimpleDiode simple1 a_node another_node


The positive points of the chosen architecture include: Analyses and models are their own independent entities. This capability leads to easy maintainability and expandability of the software. In addition, the analyses and models are easily made available through an APLAC language interface, making it straightforward to create efficient controls for the analyses that are consistently available to all models. The simulator's functionality is offered in a single consistent package with no need to simulate analyses in different simulators joined in some upper level framework or graphical user interface. In this sense, the design framework is the simulator.

On the negative side, due to messaging between objects, there is a slight performance loss in some tasks. However, because of advances in programming methods and computer hardware power, the loss in speed is near negligible. Also, users that are accustomed to other simulators sometimes have difficulties in realizing the approach and architectural implications of the APLAC simulator.


Basic software architectural guidelines of the APLAC circuit simulator program were presented. A fundamental element, VCCS was described, and the methods of how models are derived from simple VCCSs were reviewed. Analysis implementation on the models was also examined. Finally, controls governing complex analysis tasks based on the APLAC language, and the possibility to define arbitrary models that operate in every analysis method were reviewed. In particular, it has been emphasized that the simple nodal DC analysis of circuits having only independent or linear VCCSs is adequate for simulating even the most complicated circuits or systems. Object orientation allows a rigorous utilization of simple components as building blocks of more complex ones. The designer has the liberty to choose either to build his models directly from VCCSs, or to utilize more advanced building blocks, such as, already existing components like resistors. Since every component of APLAC works with every analysis mode, all components are truly available.

Moreover, the functionality of the code is well encapsulated, with very little fear of side effects as the code is developed further. The object-oriented regime also opens up new vistas in algorithm development since the control of the algorithms is brought down from the system level to the individual models composing the system equations.


The material in the article relates directly to the APLAC computer program offered for sale by APLAC Solutions Corp., Espoo, Finland. Additional reference material is available on the Web at publications.


1. M. Valtonen, "APLAC - A Flexible DC and Time Domain Circuit Analysis Program for Small Computers," Helsinki University of Technology, Radio Laboratory, Report S56, 1973.

2. M. Valtonen, "APLAC - A Frequency Domain Program for Microwave Circuit Analysis and Design," Twente University of Technology, Microwave Laboratory, Report 1252-79-05, 1979.

3. M. Valtonen and T. Veijola, "APLAC - A Microcomputer Tool Especially Suited for Microwave Circuit Design in Frequency and Time Domains," Proceedings of URSI/IEEE National Convention on Radio Science, Espoo, 1986, p. 20.

4. M. Valtonen, P. Heikkilä, A. Kankkunen, K. Mannersalo, R. Niutanen, P. Stenius, T. Veijola, and J. Virtanen, "APLAC - A New Approach to Circuit Simulation by Object Orientation," Proceedings of the 10th European Conference on Circuit Theory and Design, Vol. I, Copenhagen, 1991, pp. 351-360.

5. M. Valtonen, P. Heikkilä, et. al., "APLAC - An Object-Oriented Analog Circuit Simulator and Design Tool," Helsinki University of Technology, Circuit Theory Laboratory and Aplac Solutions Corporation,7.51 User's Manuals and Reference Manuals, 1999.

6. P. Heikkilä, "Object-Oriented Approach to Numerical Circuit Analysis," PhD dissertation, Helsinki University of Technology, 1992.

7. J.Vlach and K.Singhal, Computer Methods for Circuit Analysis and Design, Van Nostrand Reinhold, 1983.

8. A.R. Djordjevic, K.S. Tapan and R.F. Harrington, "Analysis of Lossy Transmission Lines with Arbitrary Nonlinear Terminal Networks," IEEE Transactions on Microwave Theory and Techniques, Vol. MTT-34, No. 6, June 1986, pp. 660-666.

9. P. Stenius, P. Heikkilä and M. Valtonen, "Transient Analysis of Circuits Including Frequency-dependent Components Using Transgyrator and Convolution," Proceedings of the 11th European Conference on Circuit Theory and Design, Part II, Davos, 1993, pp. 1299-1304.

10. T. Aprille and T. Trick, "Steady State Analysis of Nonlinear Circuits with Periodic Inputs," Proceedings of the IEEE, Vol. 60, January 1972, pp. 108-114.

11. A. Brambilla, E. Dallago and D. D'Amore, "A New Numerical Method for Steady State Circuit Analysis," Proceedings of the 11th European Conference on Circuit Theory and Design, Davos, 1993, pp. 1671-1676.

12. S.A. Maas, Nonlinear Microwave Circuits, Artech House, 1988.

13. G.B. Sorkin, K.S. Kundert and A. Sangiovanni-Vincentelli, "An Almost-periodic Fourier Transform for Use with Harmonic Balance," International Microwave Symposium Digest, 1987, pp. 717-720.

14. Demir and A. Sangiovanni-Vintelli, Analysis and Simulation of Noise in Nonlinear Electronic Circuits and Systems, Kluwer Academic, 1997.

15. K. Kundert, J. White and A. Sangiovanni-Vincentelli, Steady-state Methods for Simulating Analog and Microwave Circuits, Kluwer Academic, 1990.

16. V. Rizzoli, C. Cechetti, A. Lipparini and F. Mastri, "General-Purpose Harmonic Balance Analysis of Nonlinear Microwave Circuits Under Multitone Excitation," IEEE Transactions on Microwave Theory and Techniques, Vol. 36, December 1988, pp. 1650-1660.

17. "Introduction to RF Simulation and its Application," IEEE Journal of Solid-State Circuits, Vol. 34, No. 9, September 1999, pp. 1298-1319.

18. R.K. Brayton, G.D. Hachtel and A.L. Sangiovanni-Vincentelli, "A Survey of Optimization Techniques for Integrated Circuit Design," Proceedings of the IEEE, Vol. 69, October 1981, pp. 1334-1362.

19. R.K. Brayton and R. Spence, Sensitivity and Optimization, Elsevier Scientific Publishing Company, 1980.

20. H. Gaunholt, P. Heikkilä, K. Mannersalo, V. Porra and M. Valtonen, "Gyrator Transformation - A Better Way for Modified Nodal Approach," Proceedings of the 10th European Conference on Circuit Theory and Design, Vol. II, Copenhagen, 1991, pp. 864-872.

21. M. Valtonen, P. Heikkilä, H. Jokinen and T. Veijola, "APLAC - Object-Oriented Circuit Simulator and Design Tool," Chapter 9 (40 of 1028 pages) of Low-Power HF Microelectronics - A Unified Approach, Editor: G. Machado, IEE Circuits and Systems, IEE London, 1996.

22. J. Roos and M. Valtonen, "Modified Nodal Formulation Method Applied to Piecewise-Linear DC analysis," Proceedings of ISCAS'98, Vol. 3, Monterey, 1998, pp. 403-406.

23. M. Lähepelto and M. Valtonen, "Measurement-based MESFET Model Generator with the Use of a Novel Optimization Strategy," International Journal of Microwave and Millimeter-wave Computer-aided Engineering, Vol. 7, No. 1, January 1997, pp. 75-82.

24. C. Michael, H. Su, M. Ismail, A. Kankkunen and M. Valtonen, "Statistical Techniques for the Computer-aided Optimization of Analog Integrated Circuits," IEEE Transactions on Circuits and Systems, Vol. 43, May 1996, pp. 410-413.

Olli Pekonen is a Doctor of Science in electromagnetics with a degree from the Helsinki University of Technology. He is currently R&D Manager at Aplac Solutions Corp.

Martti E. Valtonen received the Dipl Eng, Lic Tech, and Dr Tech degrees in electrical engineering, from the Helsinki University of Technology. From 1978 to 1979, he was a research fellow at the Twente University of Technology, Enschede, The Netherlands. Since 1982, he has been a professor of electrical engineering at the Helsinki University of Technology, engaged in the teaching and research of circuit theory and CAD. He is the main author of APLAC circuit design tool.

Arvi Karhumaki is a technical writer at Aplac Solutions Corp. He is studying part-time at the Helsinki University of Technology, department of electrical engineering.

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