Millimeter Wave Passive Bandpass Filters

This article provides a comprehensive review of millimeter wave (mmWave) passive bandpass filters (BPF). A detailed discussion is provided on different topologies and architectures, performance comparisons, design challenges and process technologies. Passive BPFs offer the advantages of high operating frequency, good linearity, low noise figure (NF) and no power dissipation. Careful consideration of available process technologies is required for the implementation of high performance mmWave circuits. GaAs and InP (group III-V) processes provide high cutoff frequencies (fT), good noise performance and high quality on-chip passives. The CMOS process has the prominent advantages of low cost, a high degree of integration and high reliability, while the SiGe BiCMOS process demonstrates high fT, a high level of integration, and better noise and power performance.

The mmWave band of the electromagnetic (EM) spectrum spans from 30 to 300 GHz. The free space wavelength for this spectrum is in the mm range (1 to 10 mm). Worldwide availability of unlicensed frequency bands around 60 GHz makes the mmWave band very attractive for high speed wireless data transfer at multi-gigabits/second (Gbps).1 The operating frequencies of wireless communication systems have increased rapidly with the continuous growth in communication technology. Owing to the development of mmWave transceivers, high speed data transfers through wireless local area networks, wireless home networks, and wireless personal area networks is possible.

Figure 1

Figure 1 A bandpass filter is typically used at the front-end of an RF receiver.

In these communication systems, filters are essential front-end components for signal selection at specific frequencies. Their electrical responses are critical for overall system performance. A BPF allows in-band signals and sufficiently rejects unwanted out-of-band signals. In a radio frequency (RF) receiver, a BPF is situated between the antenna and the low noise amplifier (LNA), as shown in Figure 1.

A BPF of small size, with a high quality factor (Q-factor), low NF, low insertion loss (IL), high return loss (RL), good selectivity and high out-of-band rejection (stopband rejection) is required to improve the performance of an RF receiver. In general, systems can be divided into two categories: system-on-chip (SOC) and system-on-package (SOP). In SOC, all the functions of a complete system, including digital, analog, RF and others, are implemented in a single integrated circuit (IC). SOP, a system-level package, contains multiple ICs for the realization of entire system functionality. In the mmWave spectrum, monolithic ICs are preferred over hybrid ICs because of cost, size, reliability, reproducibility, design flexibility and level of integration issues. Off-chip BPFs are not suitable for modern high speed wireless transceivers because they are bulky and expensive. The elimination of off-chip components reduces the size and cost of a system; therefore, the development of new design techniques for on-chip implementation of the components previously designed off-chip is a major driving force for advanced communication systems.2

BPFs can be classified into three categories: purely active, purely passive and active (active + passive or semi-passive).3 The principal advantage of purely active BPFs is small size, but their operating frequencies are low, and they also suffer from poor linearity, high NF and high power dissipation. Purely passive BPFs can be operated at high frequencies, and have good linearity, low NF and zero power dissipation, but require a large silicon (Si) area. The characteristics of active BPFs are medium operating frequencies, poor linearity, high NF, medium power dissipation and a smaller area than that of passive filters. Table 1 summarizes the features of the three BPF types.

Table 1

The manufacturing technologies commonly used for RF filters include MMIC, low temperature co-fired ceramic (LTCC) and printed circuit board (PCB). Various fabrication process technologies are used, including Si microelectromechanical systems (Si MEMS), GaAs, GaAs MEMS, Si benzocyclobutene (Si BCB), SiGe, integrated passive device (IPD), liquid crystal polymer (LCP) and CMOS.

GaAs and InP (III-V technologies) processes demonstrate better performance than the CMOS process because of higher breakdown voltages, higher electron mobilities, and high quality passives.4 These processes offer high cutoff frequencies (fT) and good noise performance. However, high cost, a low level of integration and high power dissipation are the major drawbacks of the III-V semiconductor technologies.

Low cost, a high integration density, simple fabrication steps, scaling capability and good reliability are the main advantages of the CMOS process through which digital, analog, and RF modules may be integrated in a single chip. Continuous scaling of CMOS technology has produced MOS transistors that have cutoff frequencies beyond 100 GHz. With MOSFET scaling, fT and the maximum oscillation frequency (fmax) are both increased. Scaling improves the speed and noise performance of MOS transistors.

Because of the low resistivity of Si substrates (typically 10 Ω-cm) used in mmWave circuits, on-chip passive components exhibit low Q-factors and suffer from high losses in the CMOS process. Substrate and metal losses are severe issues, as well. In addition, polysilicon is used as the gate material in CMOS devices. The sheet resistance of polysilicon (approximately 10 Ω/sq) is much higher than that of metal, which consequently increases the MOSFET gate resistance. The high gate resistance can decrease MOSFET power gain and increase noise. Noise is a severe problem in CMOS RF circuit design. By using layout techniques, the effects of the polysilicon gate can be reduced.4 All the factors mentioned above cause degraded BPF performance in areas such as IL, RL and out-of-band rejection.

Similar to the CMOS process, the SiGe bipolar CMOS (BiCMOS) process also provides high fT and fmax. In addition, SiGe heterojunction bipolar transistors (HBT) display superior noise performance and better transconductance. The SiGe BiCMOS process is the most suitable contender for low noise, low power, high density and low cost RF circuit design.


The size of a mmWave passive filter is smaller than that of a filter at microwave frequencies. This supports the integration of mmWave passive filters with other circuits on a single chip and helps in developing miniaturized systems at lower cost.5

Figure 2

Figure 2 Distributed quasi-TEM transmission line model.4

The Q-factor of a monolithic transmission line (TL) is directly proportional to the square root of its operating frequency. Thus, with increasing frequency, the Q-factor of a TL is enhanced. Consequently, TLs are broadly used and preferred as resonators for mmWave passive filter design.6 Below 30 GHz, passive filters based on lumped circuit elements are more compact than filters realized with TLs. Above 30 GHz, lumped elements filter implementations demand exact models and manufacturing techniques with high precision. Around and above 60 GHz, TL based implementations are more suitable for monolithic passive filter design.7

At mmWave frequencies, reactive elements required for matching networks and resonators become very small. Quasi-transverse electromagnetic (quasi-TEM) TLs are easily scalable in length and can realize small reactances. In addition, the modeling of TL based interconnects is simple. Another advantage is that their well-defined ground return path reduces electric and magnetic field coupling to adjoining structures.4 Figure 2 shows the distributed circuit model for the quasi-TEM TL. This TL can be characterized by using Equations 1-4.

Equations 1-4

Where R, L, G and C are the resistance, inductance, conductance and capacitance per unit length, respectively; Z0 and λ are the characteristic impedance and signal wavelength for a lossless (R = G = 0) TL; ω0 is the resonant angular frequency; QL is the inductive quality factor and QC is the capacitive quality factor. TLs on conductive Si substrate have low values of QC because of the effect of substrate coupling, while QL is the most crucial parameter for determining TL loss.

Table 2

In recent years, many efforts have been made to implement mmWave lumped passive filters. A number of integrated miniature mmWave lumped BPFs are available in literature. BPFs with spiral inductors and metal-insulator-metal (MIM) capacitors are realized by Dehlink et al.,8 and Lu et al.9 BPF design using interdigital capacitors is reported by Vanukuru et al.10 For the realization of very small capacitance values, interdigital capacitors are preferred. Compared to interdigital capacitors, MIM capacitors have lower Q-factors owing to high dielectric losses at mmWave frequencies. Since filters with interdigital capacitors do not involve MIM processing, process cost can be significantly reduced. Nonetheless, the area of a MIM capacitor is much smaller. Because of the larger size of an interdigital capacitor, associated parasitic inductances are increased, which affect device performance.10 Table 2 summarizes the comparison between MIM and interdigital capacitors.


The topologies of mmWave passive BPFs reported in the literature include coupled-line,2,11 ring resonator12,13 and stepped impedance resonator.14,15 The planar π-filter configuration has shown the advantage of bandwidth (BW) insensitivity to layout and substrate thickness variations for different processes, such as PCB,16 GaAs substrate,17 and Si substrate.18 This configuration, therefore, displays a larger design margin. However, there are two drawbacks to the planar π-filter structure: a relatively large area and difficulty in SOC integration. These disadvantages can be avoided by using compact microstrip line (MSL) inductors.9 Figure 3 shows the schematic of a CMOS passive BPF with a planar π-filter configuration. Miniature on-chip MIM capacitors and MSL inductors are used for realizing the miniaturized BPF.

Figure 3

Figure 3 Miniaturized CMOS passive BPF with a planar π-filter configuration BPF.9

The performance parameters of previously published passive BPFs are compared by several authors.2, 6, 9, 10, 19-21 Table 3 summarizes the performance of various mmWave passive BPFs, where fc is the center frequency. The 3 dB BW is also known as the 3 dB fractional bandwidth (FBW) as defined in Equation 5.

Math 5

Passive filters have a significant drawback of high loss. The Q-factor of a passive resonator is degraded owing to ohmic (metal), dielectric and radiation losses. The bulky structure of passive waveguide filters increases the size of the fully integrated transceiver module. Passive planar filters are small in size but suffer from losses.

Table 3

Other critical drawbacks associated with passive filters include incompatibility with tunable elements and the trade-off between BW and IL. Various limitations and design challenges of mmWave passive BPFs in CMOS process are analyzed and explained by Mouthaan et al.21 In the literature, no CMOS passive filter has been reported with 3 dB FBW below 10 percent or above 65 percent. Filters with FBWs below 20 percent experience high losses. Therefore, the realization of narrowband passive BPFs with low IL is a crucial design challenge. Another design challenge is the implementation of passive filters with high out-of-band rejection levels.


This review discusses the merits, demerits, design techniques, topologies and design challenges of mmWave passive BPFs. The salient shortcomings of on-chip passive BPFs include high loss and a trade-off between BW and IL. Various process technologies for the implementation of mmWave filters are also discussed and compared in detail. This review should help researchers to identify the gaps and provide motivation for future development in the area of mmWave filter design.


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Saurabh Chaturvedi (MIEEE) completed his B.Tech. in Electronics and Communication Engineering (ECE) at the Jaypee Institute of Information Technology (JIIT), NOIDA, India (2001-2005). He obtained the M.Tech. degree in VLSI Design from the Centre for Development of Advanced Computing (CDAC), NOIDA (2006-2008). He then worked with the SPB R&D group of Cadence Design Systems, NOIDA (2008-2009). In July 2009, Saurabh became a faculty member in the ECE Department of JIIT and taught at undergraduate and postgraduate levels. He joined the University of Johannesburg (UJ), South Africa in May 2015, and is currently working towards his Ph.D. degree in electrical and electronic engineering. His current research is focused on mmWave IC design.

Mladen Božanic (SMIEEE) obtained his B.Eng. and Ph.D. degrees in electronic engineering from the University of Pretoria (UP), South Africa. In 2008, he joined Azoteq, a fabless IC design company originating in South Africa where he has been responsible for the silicon-level design, simulation and characterization of various analogue, RF, digital and mixed-mode circuits. He is also playing the role of a design for testability (DFT) engineer. He is currently with the University of Johannesburg (UJ), serving as a senior research fellow, where his areas of interest include RF, microwave and mmWaves. He is an author or co-author of over 10 peer-reviewed journal and conference articles, one book and one book chapter.

Saurabh Sinha (SMIEEE, FSAIEE, FSAAE) obtained his B.Eng., M.Eng. and Ph.D. degrees in electronic engineering from the University of Pretoria (UP), South Africa. Prof. Sinha served the UP for over a decade, with his most recent service as director of the Carl and Emily Fuchs Institute for Microelectronics, Department of Electrical, Electronic and Computer Engineering. On 1 October 2013, Prof. Sinha was appointed as executive dean of the faculty of engineering and the built environment (FEBE) at the University of Johannesburg (UJ). As a published researcher, he has authored or co-authored over 75 publications in peer-reviewed journals and at international conferences, and is the managing editor of the South African Institute of Electrical Engineers (SAIEE) Africa Research Journal.

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