- Buyers Guide
A Fast Switching, Low Noise, Indirect Synthesizer
The FastSource frequency synthesizer, which covers the 4.5 MHz to 6 GHz frequency range with a switching speed of less than 100 µs, is featured on this month's cover
A Fast Switching, Low Noise, Indirect Synthesizer
The dilemma faced by automatic test equipment suppliers in the test of multifunction ICs for the wireless industry is that they require the spectral purity of indirect synthesizers for LO and stimulus signals. At the same time, switching speeds of direct synthesizers are also required to achieve throughputs commensurate with high volume IC production. Most indirect synthesizers are designed for good spectral purity and frequency resolution while their switching times are on the order of 1 to 10 ms or higher. On the other hand, direct synthesizers are capable of good phase noise performance at frequency offsets below 1 MHz but tend to be excessive above 10 MHz, thus limiting their use as an LO. However, direct synthesizer switching speeds vary from 200 ns to 10 ms, orders of magnitude faster than their indirect counterparts. Direct configurations also can cost significantly more than indirect models.
The FastSource fast switching frequency synthesizer represents a milestone in synthesizer development. The unit is designed specifically to meet the needs of today's telecommunications industry, providing a cost-effective solution without sacrificing performance. The new synthesizer covers the 4.5 MHz to 6 GHz frequency range with a switching speed of less than 100 ms. In addition, the unit's phase noise at 1 GHz is better than -125 dBc/Hz at 100 kHz offset and spurious levels are better than -65 dBc. Table 1 lists the synthesizer's key performance specifications.
Frequency Range (MHz)
4.5 to 6010.0
Step Size (Hz)
Power Output (dBm)
Switching Time (micro-sec) to within 1 radian of final phase
Output phase noise (1 to 2 GHz) (dBc/Hz)
Spurious (4 to 2000 MHz) (dBc) (max)
In selecting a design approach, foremost consideration was given to phase noise performance and switching speed requirements. A multiloop design was chosen over a single-loop configuration to meet the 1 Hz resolution criterion. An output loop frequency range of 1 to 2 GHz is beat down to a narrower VHF range using a stepped LO where a low noise variable-frequency reference is generated. The LO comprises a 100 MHz crystal oscillator and amplifier driving a step-recovery diode comb generator, and exhibits a phase noise level that is at least 3 dB below the system noise specification.
Using the 100 MHz comb, an LO signal is generated in 50 MHz steps via a VCO phase-locked 25 MHz above and below each 100 MHz comb line, as shown in Figure 1 . Figure 2 shows an example of how the oscillator's phase noise performance exceeds the specification at 1 MHz offset and beyond, resulting in a loop bandwidth of 1 MHz. This wide phase-lock bandwidth contrasts with the 10 to 100 kHz loops used in most commercial instruments, and is certainly wide enough to achieve an 80 ms lock-up time.
The 1 MHz loop requires care in the choice of loop components to maintain stability. The VCO features a wide modulation bandwidth of at least 25 MHz to ensure loop stability. Two VCOs are used to cover the octave range and minimize tuning sensitivity.
The loop's low noise loop amplifier has a 120 MHz bandwidth. The optimum loop bandwidth was chosen at 1.27 MHz with a phase margin of 84°. At 10 kHz offset, the resulting noise is -130 dBc/Hz, 5 dB better than the requirement. At 100 kHz, the noise is -131 dBc/Hz, a margin of only 3 dB to the specification. At this point, the noise is largely that of the phase detector (a limitation of this device).
Figure 3 shows the overall synthesizer block diagram. The mixer's spurious performance ensures that the 1 to 2 GHz output loop is converted to a 150 to 200 MHz IF with spurious responses lower than -70 dBc. The LO signal provides 50 MHz steps in this range with the desired noise performance and switching speed. High side injection from 1.0 to 1.6 GHz and low side injection from 1.6 to 2.0 GHz are used to reduce the required tuning range of the LO. Thus, the LO is only required to tune from 1175 to 1825 MHz, simplifying its design considerably. Switching time from 1175 to 1825 MHz is less than 24 ms.
At this point, the 1 to 2 GHz output loop is converted to 150 to 200 MHz without a significant increase in phase noise (as would be the case if a divide-by-N loop was employed). An additional LO signal is required to further reduce the frequency and range without adding noise.
The solution uses an identical 50 MHz step loop followed by a decimal divider, further reducing phase noise by 20 dB with an insignificant effect on the output loop. This signal tunes from 117.5 to 162.5 MHz in 5 MHz steps. The 50 MHz IF range is now narrowed to 5 MHz (32.5 to 37.5 MHz) and this signal is used as one input to the output loop phase detector, as shown in Figure 4 . Obviously, a synthesized reference signal covering the same range with 1 Hz steps is required for the other phase detector input.
A direct digital synthesizer (DDS) circuit is used to generate the 32.5 to 37.5 MHz reference signal and provide 1 Hz frequency resolution. Unfortunately, due to its high -40 dBc spurious level it cannot be used directly. Instead, a combination of upconversion and frequency division by 128 is used to reduce the DDS spurs to below -80 dBc. Three fixed signals are utilized in the upconversion: 540, 800 and 880 MHz. Another stepped signal is required to interpolate the 80 MHz range between the 800 and 880 MHz step. This signal is provided by a simple divide-by-N loop operating in the 1000 to 1780 MHz range with a 20 MHz resolution. The phase noise of this loop is not critical because it follows a 320 division ratio, resulting in a 50 dB noise enhancement. The loop bandwidth is designed for a band edge-to-edge speed of 25 ms.
The loop output is divided by 10 to the 100 to 178 MHz range in 2 MHz steps. This signal is injected after the 800/880 MHz conversion, thereby providing continuous coverage from 1040 to 1200 MHz. After division by 32, the output frequency is 32.5 to 37.5 MHz in 1 MHz steps, which translates to a 128 Hz resolution for the DDS. The output loop covers the 1 to 2 GHz range and drives the scalar and multiplier section to expand the range to 4 to 6010 MHz. Harmonic filtering and power leveling are accomplished in this section.
A sample of the 1 to 2 GHz signal feeds the first downconverter, and the 50 MHz step loop converts it to the 150 to 200 MHz range, which feeds the second converter. The 5 MHz step loop converts this signal to the 32.5 to 37.5 MHz range where it is applied to one input of the phase detector. The other phase detector input is from the 32.5 to 37.5 MHz reference generator. The phase detector output is loop filtered and drives the output loop VCO.
The phase noise of the output loop is, to a first degree, dependent on the noise of the 50 MHz step loop, which derives its performance from the 100 MHz comb. The 5 MHz loop and 32.5 to 37.5 MHz reference signal phase noise levels are at least 10 dB below the 50 MHz loop due to the frequency division and have little effect on overall phase noise performance. Figure 5 shows the synthesizer's phase noise at 2 GHz. Phase noise performance at 10 kHz to 3 MHz offsets is limited by the noise floor of the digital phase detectors in the output loop and the 50 MHz step loop. Switching time is better than 80 ms for any frequency transition within the overall range.
A fast switching 4.5 MHz to 6 GHz frequency synthesizer has been designed to meet the needs of today's telecommunications industry. The low noise source offers a cost-effective solution without sacrificing performance. The new synthesizer is available in a single 5.25" standard rack chassis and can be supplied in a dual configuration within that same package.
Plainview, NY (516) 694-6700.
Circle No. 302