MESFET and HEMT Design Using Fast Physical Device Simulation
Application of the HP Active Physical Device Simulator to the analysis of MESFET and high electron mobility transistor (HEMT) design issues with a focus on the physical insight that the tool offers
MESFET and HEMT Design Using Fast Physical Device Simulation
This article demonstrates how fast physical device simulation can be used in conjunction with measured data to gain insight into device operation and help troubleshoot device designs. The need for device simulation, which is fast enough to provide a reasonable level of interaction and has the ability to simulate device S parameters, is addressed. An approach that offers both these features and shows how device simulation can be applied to some active layer, cross-sectional geometry and layout design issues is outlined. In each example, measured data are provided to support the simulation results and highlight typical areas where discrepancies between experimental and simulation results occur. These discrepancies are considered to be of great value because they help the process engineer understand what has actually been made and, therefore, assist in solving typical daily problems.
Chris G. Morton
Hewlett-Packard Co., HP EEsof Division
Santa Rosa, CA
Chris M. Snowden
The University of Leeds
Today, when one talks of modeling in the microwave and RF industry, the discussion generally is focused on the extraction of an equivalent circuit from measured data. The topology of the equivalent circuit and the association of elemental values with device physical structure and operation usually spark a provoking, extensive debate. The problem is complicated by the fact that the extraction of a 16-element (or more) circuit from a single set of S parameters cannot be carried out uniquely. Therefore, either a fitting procedure must be adopted or further measurements must be performed to calculate all values uniquely.1 Either way, models cannot be examined until both the fabrication and measurement have been completed.
Physical models are different from equivalent circuit models in that they use physics to calculate the electrical characteristics of the device. Typically, that means high complexity and, therefore, longer simulation times compared to the physical models’ compact modeling counterparts. Fundamentally, physical models provide a major benefit because of their ability to link device structure to electrical performance.
For the microwave/mm-wave engineer, device performance is assessed primarily through the consideration of DC I-V characteristics (such as breakdown voltage and maximum current) and device S parameters (indirectly through ft and fmax ). Physical models that are directed at this industry must be capable of not only DC predictions, but also high frequency predictions. Real benefit is provided when the model can be used to troubleshoot designs where it is difficult to see which geometric or epitaxial parameters influence electrical performance. Physical modeling can be used in a number of ways: for investigating the suitability of a particular device design to a particular circuit application prior to fabrication, for troubleshooting existing processes using physical insight to address specific problems such as device reliability or breakdown, for enhancing designs to improve yield using sensitivity or statistical analysis techniques, for identifying why a device fails to meet electrical specifications through working back from the measured data to the physical structure of the device (reverse modeling) and for monitoring the drift of a process using automation of reverse modeling to gather data concerning the variation of device structure across a wafer.
Importantly, the model must be fast enough to provide a high level of interaction so that designs can be altered and examined quickly. Furthermore, the engineer does not want to be concerned with such numerical details as mesh generation and iterative solution schemes for nonlinear matrix problems. The model should simply take the physical structure of the device as input (in a form that the engineer understands) and compute relevant device electrical characteristics.
In this article, the HP Active Physical Device Simulator (APDS) is applied to the analysis of high electron mobility transistor (HEMT) design issues with a focus on the physical insight that the tool offers. HP APDS is organized in a hierarchical fashion, as shown in Figure 1 . The HP APDS architecture allows treatment of the device design process at three distinct stages. Capacitance-voltage and mobility profile simulations can be performed using a charge-control analysis to consider the active layer design stage. The simulation of ungated etch current vs. etch depth can be used to assist with the development of a recess process. Simulation of DC I-V characteristics can be used together with device breakdown predictions to develop cross-sectional designs. Finally, S-parameter and large-signal analyses can be performed to consider the high frequency performance of the device. Large-signal analysis is achieved through the generation of a simulation-based root model.2
An overview of the modeling techniques used in HP APDS is presented followed by several examples where physical modeling can be used to assist with the understanding of device operation and, in particular, how device geometry influences device electrical characteristics. Several examples are given where discrepancies between measurement and simulation typically are encountered. How physical modeling can be used to identify differences between the intended and actual physical structure of the device is demonstrated by indicating how correlation between measurement and simulation can be achieved. Many would suggest that such discrepancies indicate the inaccuracy of the model. However, it can be argued that discrepancies can be extremely informative, providing valuable insight when developing device prototypes. Finally, some concluding remarks regarding the scope and future of physical modeling are presented.
HP APDS uses the quasi-two-dimensional (Q2D) method,3,4 which offers substantial speed improvements over full 2-D solution schemes. The method is based on the assumption that carrier transport occurs predominantly in a single spatial dimension from the source to the drain contact. This assumption relies on the fact that the equipotential lines in the active channel of the device are parallel.
Once this assumption has been made, the electric field profile from the source to the drain can be calculated based on the propagation of a Gaussian box along the device, as shown in Figure 2 . It is important to recognize that the 2-D nature of the solution domain is maintained within the simulation through the variable height of the Gaussian box. The box height changes due to the device recess geometry, gate depletion region and transfer of carriers into the buffer or substrate. Generally, carrier transfer occurs at the drain side of the gate contact.5 Velocity overshoot is included within the numerical algorithm through a solution of the hydrodynamic equations (physics that is essential for predicting the performance of submicron devices).5
The charge within the Gaussian box is calculated from a solution of the coupled Poisson-Schroedinger equations from the semiconductor surface through to the device substrate.6 The applied gate voltage together with the Schottky barrier height define the surface boundary condition under the gate. The surface electric field defines the surface boundary condition away from the gate via the occupancy of surface states (modeled using a deep hydrogenic trap). It is important to note that the surface state occupancy across the device is not constant due to the lateral spreading of the gate depletion region and the variation in lateral electric field away from the gate depletion region, particularly on the drain side of the device.
Extrinsic effects such as capacitive coupling above the surface between gate and ohmic contacts and through the substrate between ohmic contacts, contact resistance and contact inductance are also included in the model, which is important for accurate simulation of high frequency device performance.7 Two-port S parameters are calculated using a time domain simulation to compute the Y parameters of the intrinsic device. The displacement current associated with capacitance between drain, source and gate contacts below the surface is explicitly included through the time variation of the lateral and vertical electric field components. The S parameters of the two-port device are finally computed by adding the calculated extrinsic contributions from the interelectrode capacitances, contact inductances and contact resistances. Importantly, the physical model calculates the electrical characteristics at the mesa level only. It is assumed that instrument calibration locates the reference planes of the measurement at the mesa edges when modeling results are compared with measured data.
Several examples are now provided where HP APDS can be used in conjunction with measured data to gain physical insight into device operation and to help identify differences between the specified and manufactured device structures. HP APDS provides groups of analyses that focus on active-layer, cross-sectional geometry and layout design issues. Various simulations have been implemented in the simulator for each of these stages with a view toward addressing common design and implementation problems. In the following examples, the focus is on one major implementation issue from each of the three stages.
A common problem encountered when manufacturing the active layers of a HEMT is achieving the desired doping density in the device’s electron supply layer. Most commonly, this area is located a few nanometers above the channel layer and takes the form of a very narrow and heavily doped pulse. Pulse doping offers several well-known advantages over a thicker doping layer in that it can produce a higher peak current (reduced parasitic MESFET) and higher device breakdown voltage (lower surface electric field under the gate). However, calibration of the epitaxial process usually is performed for uniformly doped layers and it is assumed that a similar dose can be introduced over a few atomic layers.
In practice, the electrically active doping density tends to be somewhat lower than the theoretical value — a common cause of discrepancies between measurement and physical device simulation. It is possible to use the device pinch-off voltage to infer the active doping density in the electron supply layer. However, factors such as access resistance and depletion region fringing effect can lead to inaccurate results.
A more informative approach is to compare the measured and simulated capacitive-voltage (C-V) response of a large-area diode in order to investigate the structure of the active layers.8 Figure 3 shows C-V measurement and simulation of a 170 x 170 m m test diode fabricated at the University of Cambridge (material supplied by the University of Glasgow). The sheet doping density in the electron supply layer directly influences the threshold voltage of the diode. In fact, alteration of the sheet doping density simply displaces the simulated response along the voltage access. The arrow indicates the displacement of the characteristic produced by a reduction in the sheet donor density of 2 x 1012 donors cm–2 .
Several important issues must be clarified in this analysis. First, the recess process utilizes a selective etch that allows for reasonably precise specification of the recess depth. When the recess process is nonselective, it is necessary to consider the C-V simulation results in conjunction with the simulation of etch current vs. etch depth in order to uniquely determine recess depth and active doping density. Second, it is assumed that the Schottky barrier height is already known (from I-V measurements) and that good morphology exists at the interface between the device channel layer and the neighboring layer above. (The shape of the C-V response can be used to identify poor interface morphology, manifesting itself as a less abrupt rise in the characteristic.) Third, it is also assumed that very little migration of the doping species takes place so that the doping layer remains distributed over only a few atomic layers. This condition also is indicated in the diode response (after the knee) through a much sharper rise in the capacitance than shown in the simulated response. A profile of the channel carrier density and conduction band edge, shown in Figure 4 (either under the gate or at points around the recess), can be used to help visualize and understand some of these practical issues. In this case, the profile is taken near the source of the device and thus includes the contribution of the heavily doped cap layer.
Device breakdown voltage plays an important role in determining the performance of power amplifiers through the restriction of output voltage swing. The onset of device breakdown also has strong implications for device reliability. Figure 5 shows the comparison between measurement and simulation of a 0.1 m m InP HEMT fabricated by TRW. The simulated data have been extended to show the occurrence of device breakdown. Extension of the measured data to show the increase in current due to device breakdown is not possible because it would result in the destruction of the device.
One major factor influencing device breakdown voltage is the recess geometry on the drain side of the device together with the doping density and thickness of the heavily doped cap layer. Figure 6 shows an example of device profiles calculated using HP APDS. The sharp peak in electric field directly under the recess edge clearly indicates the role that this geometric feature plays in defining device breakdown. The electric field profile is sharp due to an abrupt transition in the sheet carrier density across the recess edge. Choice of both recess geometry, cap and channel electron supply layer doping densities and layer materials together influence the characteristics of this transition and, therefore, the device breakdown voltage. It can be inferred that electrical stability of the surface in the region of this transition is important for maintaining stable device characteristics since it defines the surface electric field.
Figure 7 shows the measured and simulated S parameters of the device from 1 to 40 GHz and at a gate bias of +0.2 V and drain bias of 0.1 V. In this case, good agreement is observed between the measured and simulated data. However, simulation of the device using the specified recess opening produced quite a large discrepancy in the position of S22 . A change of a few nanometers in the recess opening displaces the S22 response along the real axis of reflection coefficient as depicted by the arrows. Therefore, the initial discrepancy between measurement and simulation again proves to be informative. In this case, it reveals a sensitivity of the device output conductance to the recess opening, an effect that finds its origin, again, in the location of the high field region close to the recess edge on the drain side of the device.
It is important to note that agreement in the DC I-V characteristics is a necessary but insufficient condition for achieving agreement in the device S parameters. The time-varying electric field throughout the device gives rise to a displacement current, which, obviously, is not resolved in the DC I-V characteristics but strongly influences the device S parameters. Therefore, it is incorrect to assume that a good device model is obtained based solely on the agreement between measured and simulated DC I-V characteristics.
When comparing simulated and measured S parameters, it is common for discrepancies to occur simply due to inappropriate location of the reference plans in the measurement or directly as a result of errors in the calibration procedure. The layout of a pseudomorphic HEMT fabricated at the University of Cambridge (material supplied by the University of Glasgow) is shown in Figure 8 . Three different device sizes have been chosen that have 2 x 20 m m, 2 x 40 m m and 2 x 60 m m gate widths. The three devices utilize a 0.12 m m gate and have been designed specifically for use in the range from 75 to 110 GHz (W band). In each case, 200 m m feeds are used to make the transfer from the probe contact point and taper discontinuities on either side of the structure to the edge of the device mesa.
Network analyzer calibration was performed using the line-reflect-line (LRL) variant of the thru-reflect-line procedure. This method is particularly well suited to coplanar waveguide technology, which offers extremely low dispersion when the line is designed correctly. The main task then is to determine the characteristic impedance of the line used to set the reference impedance for the measurement (in this case, to 50 W ).9
The through standard of the LRL procedure is used to set the reference planes of the measurement to the edge of the device mesa and, therefore, is 400 mm long. The issue of reference plane location is important when comparing physical device simulations since it can lead to misinterpretation of the comparison of measured and simulated results. For example, reference plane location just after the probe pad taper would introduce an extra delay associated with the 200 m m feeds, leading to a significant phase shift of the two-port reflection coefficients in this frequency range.
Figure 9 shows the comparison between measured and simulated S parameters of the 2 x 60 m m device from 75 to 110 GHz at gate- and drain-source voltages of –0.25 and 2 V, respectively. In this example, it is informative to consider the frequency range from 75 to 110 GHz because it helps to bring out differences between simulation and measurement that are not resolved at lower frequencies. It can be seen that good agreement is achieved between measurement and simulation but that this agreement was only possible after a significant adjustment had been made to the interelectrode capacitance between the gate and drain contacts. In this case, the calculated value of approximately 1 fF was increased to 5 fF and produces an approximately fixed displacement of the S parameters by an amount depicted by the arrows.
The calculation of the gate-drain interelectrode capacitance is difficult to carry out because it is necessary to model the complicated geometry of the gate metallization. It is important to note that a similar error exists in the calculation of the interelectrode capacitance between source and gate. However, the intrinsic gate-source capacitance is much larger than that from the interelectrode coupling, which makes the error less pronounced.
It might be concluded that accurate modeling of the device over this frequency range is not possible with HP APDS, which is in part true. However, the ability of the tool to separate out the contributions to the electrical characteristics of different aspects of the device structure still allows the designer to make informed decisions based on useful physical insight. Figure 10 shows results for the 2 x 20 m m device. In this case, the modified gate-drain interelectrode capacitance used for the largest device was scaled in accordance with these two mesa sizes. Putting aside the manual scaling of gate-drain interelectrode coupling, adjustment of the gate width automatically accounts for all of the scaling rules that normally would have to be applied to each element of the equivalent circuit.
Several examples have been presented where physical device simulation can be used in conjunction with measured data to gain physical insight into device operation. Using specific examples, common causes of discrepancies between measured and simulated data were highlighted and how these differences can be extremely informative was demonstrated. It is unreasonable to insist on an exact match between the measurement and simulation results through blind comparisons simply because process variation across a wafer will naturally lead to differences even between measured data from devices in different positions on the mask.
Physical modeling can be used prior to fabrication in an attempt to quantify the suitability of a device design to a particular circuit application. The process also offers great promise in the area of yield-driven design using statistical analysis because of the direct link the method provides between device structure and electrical performance. However, the main benefit to the engineer initially will be in the ability of fast physical modeling to assist with troubleshooting existing designs. This procedure will allow more informed decisions to be made regarding which design parameters to focus on and, therefore, will help to reduce the development time of new devices and circuits.
The authors wish to thank TRW for providing device data, the University of Cambridge and the University of Glasgow for the manufacture of devices and calibration standards, Roger D. Pollard for his informative discussions, and the Defense Advanced Research Projects Agency (MAFET Thrust 1 activity) and Engineering and Physical Sciences Research Council for providing funding for this work. n
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