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Industry News

Don't Rule Out the MESFET!

The maturation of implanted GaAs MESFET technology, which supports key criteria for successful wireless products

July 1, 1998
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Don't Rule Out the MESFET!

Wes Mickanin
TriQuint Semiconductor
Hillsboro, OR

The rapid increase in the number of wireless technology applications has finally launched the GaAs semiconductor industry onto a steeper growth curve. A variety of GaAs technologies compete for the best position with glowing reports of state-of-the-art devices and performance. Practical users look beyond the hyperbole to history, yields, price, levels of device/circuit integration and delivery to select suitable products for their application. The mature implanted GaAs MESFET technology has continued to evolve and improve, and supports all of these key criteria for successful wireless products.

Device Performance

Discrete transistors always have the best performance - a fact well established in advanced technology. Discrete processes allow beyond-cutting-edge process technology where the huge numbers of devices per wafer compensate for the small wafer or substrate size and inevitable yield loss, not to mention the optimization of each device to the specific circuit application. Unfortunately, the burden of integration, process variability, parasitic control and detailed subsystem design falls on the shoulders of the designer for each generation of products (in addition to the constraints of size and packaging).

With 18-month product generations and rapidly increasing system complexity, complex subsystem design is costly and time-consuming. In today's wireless systems, total system capability, cost and time to market are the key criteria. MESFET, psuedomorphic high electron mobility transistor (PHEMT) and heterojunction bipolar transistor (HBT) devices are all capable of meeting the fundamental technology requirements. Even advanced silicon technologies such as laterally diffused metal-oxide semiconductor (LDMOS), Si bipolar and SiGe demonstrate increasing promise, as listed in Table 1 . Each technology has its strengths, but it is the application of the technology strengths to the design problem that is often critically missing.

Table I
Device Technology Comparison

Capability

Implanted MESFET

PHEMT

HBT

Bipolar

LDMOS

Multiple Thresholds

++

-

N/A

N/A

++

Intergration Level

++

+

 

++

++

3V operation ³

Good

Good

Vbe limited

Vbe limited

Poor

External MOS switch req.

Yes

Yes

No

No

Yes

Volume IC Production Experience

Extensive

Small

Small

Extensive

Small

Cost

Low

High

High

Very low

Low

Maximum Operating Temperature

++

++

-

-

-

Wafer Size (mm)

100

100

100 for GaAs,
75 for InP

100 to 150

100 to 150

External Negative bias required

No

Yes

No

No

No

External supply sequencing

No

Yes

No

No

No

Tj (max) C °

150

150

125

125

125

Cost of on-chip passives

Medium

High

High

Low, hard to integrate

Low, hard to integrate

Today's sophisticated users do not make purchasing decisions based on Idss , ft or Gm any more than a PC purchaser buys based on metal pitch or Leff . Instead, the focus is on cost and performance. The maturity of ion-implanted MESFET technology produces leverage in device optimization, technology flexibility, yield and cost. Processes such as fourth-generation TQTRx MESFET technology can provide triple-threshold FET technology- enhancement- and depletion-mode (E/D) devices integrated with robust power FETs at low cost and high volume. This technology can economically provide integrated control and bias functions as well as power devices optimized for 3 V operation. Low voltage power amplifier (PA) operation demands low knee voltage, linear Gm, high current drive and robust breakdown voltages, as shown in Figures 1 and 2 for a 300-m m-wide power FET. Combined with optimized enhancement-mode (normally off) and depletion-mode (normally on) control logic, the overall process produces a fully planarized topology and highly flexible 20 GHz device architecture. Table 2 lists a TQTRx device overview.2

Table II
TQTRx - Implanted MESFET Performance

Parameter

E-mode FET

D-mode FET

Power FET

Vth , Vp (V)

0.15

-0.60

-2.20

Imax (mA/mm)

90

240

400

Idss (mA/mm)

N/A

70

270

ft at Imax /2 Idss /2 (GHz)

18

18

18

Gm at Imax /2 Idss /2 (GHz) (mS/mm)

265

150

150

Breakdown voltage (avalanche) (V)

> 16

> 13

> 15

While using a mature 0.6 m m gate length I-line stepper lithography process for good yield, it is clear that MESFET devices have not come close to the limits of lithographic scaling. Integrated and highly efficient charge pumps using E/D FETs provide power supply sequencing and allow optimization of the power device threshold (Vp = -2.2 V). In turn, these processes provide high Idss (270 mA/mm) and good Imax (400 mA/mm) while achieving an avalanche breakdown voltage of well over 15 V.

Process Integration

Top system designers look at the functional capability of the product to determine if it is a collection of discretes, a couple of transistors in a box or a true integrated RF function block with minimal external support requirements and the RF expertise and characterization to back up the specifications. Fully integrated functions demand good performance in all areas. However, above all, the functions demand true RF integration to meet customer performance and size requirements. Power output capability, easy power control, thermal and RF stability, and good reliability are key contributors to a device's ease of use. However, none of these criteria is more important than achieving the lowest system solution cost. For example, the high throughput of modern implanters allows over 1500 channel and contact implants per week.1

In addition to the high manufacturing flexibility, implantation allows inventory costs to be minimized as the substrates can be customized on a product demand basis rather than committed to a specific process flow and stockpiled in advance (as in the case of epitaxial wafers). Of course, silicon technology continually demands enhancement of implanter capability in the areas of wafer size, throughput, cleanliness, beam current and low accelerating voltage operation, allowing GaAs fabricators a technology free ride to future improvements. In contrast, no multithreshold epitaxial FET volume manufacturing process has been demonstrated, significantly constraining the design options of highly integrated functions.

MESFET Myths

As with any long-established technology, MESFETs get their share of gibes from the new technologies on the block (primarily HBT and PHEMT). While each of these technologies is good, they should stand on their own merits rather than on the historical limitations of MESFETs, which technological evolution has overcome today. The requirement for dual supplies for MESFETs is largely a nonissue today with efficient charge pumps, which can be more efficient than those used in silicon technology. The compact size and high performance of E/D charge pumps provide both the negative bias required for proper control of the output power FET and the supply sequencing needed for fail-safe operation.

In addition, the claim that both HBT and PHEMT technologies allow smaller die sizes due to higher performance per unit area overlooks the key fact that in today's integrated PA designs, the chip area is limited thermally (not by current density) to meet the stringent reliability goals of wireless markets. Since all the bulk substrates have the same thermal conductivity, HBT technology with a typical junction temperature limitation of 125°C for long-term reliability is at a significant disadvantage compared to the 150°C temperature limitation for MESFETs, especially in today's increasingly compact wireless handsets. Thermal analysis has shown that the aluminum-containing epitaxial layers are significantly less thermally conductive than bulk GaAs, further limiting the perceived area advantage of both HBTs and PHEMTs.3

A third limitation of implanted MESFETs often cited is the requirement for submicron lithography compared to the 1 m m feature sizes of HBTs. The development of advanced lithographic technology in the era of 0.25 m m Si and the experience of 12 years of manufacturing submicron MESFETs make the 0.6 m m gate features of TQTRx devices minimally challenging compared to the first 0.5 m m process introduced in 1986.

Finally, it has been stated that MESFETs cannot meet PA needs with 3 V supplies. While achieving a low knee voltage in a MESFET is not trivial, advances in device engineering and improved optical lithography have reduced knee voltages to acceptable levels with the potential for even more improvement with additional device scaling. The ability of either implanted or PHEMT-based FETs to completely shut down the drain current (compared to a Si MOS device) is a real limitation that currently is addressed with a very low cost external positive metal-oxide semiconductor (PMOS) MOSFET. However, advances in MESFET technology already are showing paths to remove this requirement from future process generations. While both PHEMT and HBT epitaxial-based devices are now produced routinely on 100 mm wafers, the significant additional cost of controlling the epitaxial material to high precision in thickness and doping, often at two-to-three-times bulk wafer cost, significantly limits the additional functionality that can be cost-effectively added to the chip due to the expense of the epitaxial real estate in contrast to the low cost of implanted substrates.

Passive Component Integration

While transistors receive the most emphasis, the supporting passive components of the process such as precision thin-film resistors, metal-insulator-metal (MIM) capacitors and low loss inductors often limit product performance. The precision and size of the resistors and capacitors allow optimization of circuit functions and minimization of chip area. MIM capacitors for interstage coupling and bypass functions were scaled to achieve a four-times-capacitance-per-unit-area improvement over existing processes while maintaining adequate breakdown voltage and yield. Two thick plated metal global interconnect layers with 4 and 8 m m pitch and full stacking capability optimize inductor Q (to as high as 20) and minimize resistivity (to as low as 4 mW /square) when combined with a state-of-the-art low K (2.7) dielectric - a first in high volume GaAs manufacturing.

As shown in Figure 3 , electroplated gold interconnects also provide 100 percent step coverage so that full current density capability is available in all circuit areas to address the substantial RF currents generated in these applications with minimum parasitic coupling. In addition, a local interconnect layer is available for short runs and contact to thin-film resistors. All process layers are defined by I-line stepper lithography for optimal alignment and precise critical dimension control. Reliability and environmental protection in the newest thin-profile plastic packages are addressed by multiple silicon nitride layers.

 

 

Product Design Capability

Handset manufacturers must consider more than the performance of any technology before they commit to the production of millions of units. Electrical performance is a given. Once a technology has passed that threshold, reliability, security of supply and, above all, solution cost are the criteria that separate the technologists from the suppliers. These criteria give the MESFET designer an edge by leveraging a robust technology with demonstrated reliability and volume production. Moreover, a minimum cost design is enabled by features such as triple-threshold devices, which ease logic, and mixed-signal design for bias and control circuits. Sophisticated biasing enhances device yield over process variation. Multiple global interconnect layers promote smaller die size with high density wiring as do high value MIM capacitors. True RF integration means the IC designer can incorporate the majority of RLC devices on chip, which minimizes off-chip components and reduces the solution cost. An example of a spiral inductor implementation is shown in the scanning electron microscope (SEM) photograph in Figure 4 . The circuit's passivation and interlayer dielectric have been removed for clarity.

The ability to achieve RF performance goals without the use of expensive substrate vias is another key cost consideration. The capability to thin die to minimum dimensions not only eliminates the need for vias, but also improves the thermal characteristics that reduce transistor dimensions. Planar passivation eliminates air bridges and provides silicon-like handling for packaging vendors, further reducing cost. Developing and incorporating cost-reducing features in the process architecture from the beginning provide the designer with additional degrees of freedom when converging on a minimum-cost product solution.

Manufacturing and Delivery

Once wireless products start the production ramp, the demands of consistent delivery and performance separate the promises from the facts. Every aspect of the technology path, from process sensitivities, design latitude and assembly capacity to physical dimension control, is tested severely. From bent leads to breakdown voltage, the product must conform consistently to the users' requirements.

A common concept is that things will tighten up in volume. Actually, as most experienced product engineers know, things often get worse very quickly as all parts of the component distributions are sampled in very short time scales. The intense effort that is driven by the anticipated (or sometimes actual) impact of volume production problems is what makes things tighten up in volume. There is no substitute for (sometimes painful) experience in volume ramps. During the last 10 years (and over millions of units), both in the field and in space applications, GaAs production systems have evolved to address these demands. Substantial investments are required to meet these challenges.

Future Trends

Wireless product demands are increasing with unprecedented speed. While providing opportunities for incredible growth in the GaAs industry, consistent execution of both an effective technology and volume production roadmap is required. The move to 150-mm-wafer-diameter ion-implanted GaAs MESFET technology is clearly underway and fully tested process tools are readily available.

While specialized epitaxial devices continue to provide a benchmark for performance, the continuing evolution of implanted MESFET technology will follow the established wafer size and device-scaling roadmap of silicon to provide the best possible price, performance and volume capabilities for fast-track commercial product designs. Combined with advances in low K dielectrics and advanced electroplating technology, the overall capability of MESFET-based technology will continue to provide price/performance leadership in the RF industry for high volume products.

Conclusion

The evolution of ion-implanted GaAs MESFET technology and processes over the last 10 years coupled with the manufacturing infrastructure to produce large volumes of products for consumer applications have effectively supported the rapid expansion of the wireless market. Complete RF subsystems have evolved to simplify system design tasks in the key areas of output PAs as well as low noise amplifiers and mixers. While device technology is an important factor in these designs, the overall process capability, including passive elements and wiring, is the key to providing a fully functional RF MMIC block rather than simply a collection of transistors on a chip. Assembly, packaging and RF testing in these volume applications have required robust device technologies in addition to technical innovation.

The price and delivery requirements of volume applications require sophisticated system solutions and extensive manufacturing experience in addition to the technical capability and reliability expected of the product. Future trends will demand additional functional integration and cost reductions to meet the standard set by silicon technology through the use of die shrinks, process performance improvements through device scaling and manufacturing improvements such as 150 mm wafers.

References

1. P. Fowler, "IC Technologies for Wireless Applications beyond 2000," 1997 GaAs IC Symposium Short Course, Anaheim, CA.

2. TriQuint TQTRx IC Design Manual, 1997.

3. D.E. Dawson, "Thermal Modeling, Measurements and Design Considerations of GaAs Devices," 1994 IEEE GaAs IC Symposium Proceedings, p. 285.

Wes Mickanin received his BA and MS degrees in physics and applied physics from Reed College and Cornell University in 1974 and 1976, respectively. From 1976 until 1984, he worked for Tektronix Inc. in microelectronic device testing and developed the laser

wafer-trimming process and associated design technology for high speed data converters. From 1981 to 1984, Mickanin managed the Laser Wafer Trim Group. In 1984 he joined the Tektronix GaAs Special Business Unit as a process development engineer in the dielectric deposition and etch areas. He was a member of the original process engineering team at the founding of TriQuint Semiconductor in 1995. At TriQuint, Mickanin has held a variety of positions, including program manager, test and characterization manager and, most recently, manager of the Technology Development Group responsible for new process technology development, device engineering and process integration. He is a member of the IEEE Electron Devices Society and the Materials Research Society, and has served on the technical program and executive committees of the IEEE GaAs IC Symposium.

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