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Designing High Speed Paging Systems

Solutions and approaches to the design of new pagers and the software, hardware and semiconductor products that are becoming standard in this area

May 1, 1998
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Designing High Speed Paging Systems

The area of pager systems is changing with the introduction of new paging standards, particularly FLEX, in all worldwide markets. The semiconductor concepts for new pagers are developing rapidly toward even higher integration. Single-chip concepts, including decoding, controller tasks, level shifting, frequency synthesizer and memory, are becoming common. Roaming requirements present an added level of complexity. This article examines solutions and approaches to the design of new pagers and explains the software tools, hardware platforms and semiconductor products that are becoming normal in this area.

Dominic Clancy and Evert van Veldhuizen
Philips Semiconductors
Zurich, Switzerland

Most current paging systems are based on the Post Office Code Standardization Advisory Group (POCSAG) protocol, which was designed originally for tone-only pagers and short numeric messages. The introduction of alphanumeric messaging has increased the load on airtime significantly. Operators now face a diminishing number of users per channel at a time when user numbers are rising, and no further frequency allocations for paging are likely.

Demand also is driven by new marketing approaches, such as subscription-free services, which are becoming more popular. This rise in traffic increases pressure on operators to move to higher speed paging protocols. High speed paging protocols have a number of advantages over POCSAG for operators and users, especially when existing POCSAG system base station sites can be used, which minimizes operator investment. For the end user, the most visible benefit is the large improvements in power management, which enable the pager to operate much longer from a battery.

The move toward high speed paging protocols presents new challenges to the designer. Not only is there a need to become familiar with four-level frequency-shift keying (FSK) radio, but the level of software in the new-generation pagers is significantly larger than in POCSAG. The development tools that were adequate for earlier paging standards are now insufficient. The complexity and high levels of integration in the latest high speed systems leave the designer increasingly dependent on good development tools. Without these tools, the task of developing a pager product becomes much more difficult. This article concentrates on the overall system approach, helping the designer to integrate the many functions that are now standard in pagers.

A Reference Design

A reference design is used for illustration purposes and a few guiding principles have been established. For cost reasons, the microcontroller should be a standard off-the-shelf part that is optimized for low power-down current and electromagnetic interference. The decoder should be able to interface with off-the-shelf pager receivers. Its primary function is to process information received and demodulated from the paging channel and communicate messages to the microcontroller. Many other peripheral functions also may be included in the decoder. The receiver in this reference design is a classical double-superheterodyne receiver. Alternatively, it could use a zero-IF concept, which is the lowest cost approach available but must be suitable for two- and four-level FSK modulation.

The block diagram of the solution is shown in Figure 1 . The system uses I2 C architecture for the control of the ancillary circuits with the advantages of a wide choice of low cost circuits, tools and drivers that exist for this architecture.

Functional Blocks

The Receiver

The receiver front end consists of discrete components, and the receiver back end consists of an IF and demodulator. In this development design, an RF generator also may be connected to the receiver. The PCB is prepared for a loop antenna. Of course, the design of the antenna is important, and development tools are available to make this task easier. Parts of the receiver may be switched on and off using the receiver control lines, which are controlled directly from the decoder.

If a zero-IF solution is preferred, then care must be taken to avoid the problems that are often experienced with self-reception. The receiver must be constructed carefully and the overall pager design must generate very little noise. However, attention to these details will produce a zero-IF pager that is sensitive enough to meet the requirements of the user and the pager network operator.

The block diagram of the receiver part is shown in Figure 2 . The front end is a discrete circuit. The second mixer, quadrature detector, data filter, level comparators and 1 V regulator are integrated into the IF IC. Table 1 lists the receiver’s characteristics.

Table I
System Performance

Parameter

Conditions

Requirement

Sensitivity (dBm)

6400 baud, four level, BER = 3%
1600 baud, two level, BER = 3%

< -122
< -125

Sensitivity Degradation;
compared to B+ = 1.3V (dB)

B+ = 1.1 V;
B+ = 1 V

< 3
< 6

Adjacent-Channel selectivity (dB)

± 25 kHz offset
± 37.5 kHz offset
± 50 kHz offset

> 60
> 60
> 60

Second-order IM rejection (dB)

Threshold +3 dB

> 52

Third-order IM rejection (dB)

Threshold +3 dB

> 52

Blocking Immunity (dB)

Threshold +3 dB;
frequency range 1 to 10 MHz in
1 MHz steps

> 70

Spurious rejection (dB)

Threshold +3 dB; frequency range 100 kHz to 2 GHz

> 60

Image rejection (dB)

Threshold +3 dB; first IF
Threshold +3dB; second IF

> 50
> 50

Co-channel (dB)

Threshold + 3 dB

< 7

Frequency offset range (kHz)

For 3 dB degradation in sensitivity
For 6 dB degradation in sensitivity

> 3
TBF

Spurious output levels (dBm)

Available power at RF amplifier input of testboard into 50W load at carrier frequency

< -75

The Baseband Section

The baseband section contains the decoder, the host microcontroller, a 256-byte electrically erasable programmable read-only memory (EEPROM), alerters (beeper and light-emitting diode (LED)), liquid crystal display (LCD) and 8 kB static random access memory (SRAM) plus DC/DC conversion. The data input is selected from the receiver or from a signal generator.

The system is powered directly by one AAA battery via a smoothing coil so the minimum operating voltage is 1 V. For the baseband board, a DC/DC converter boosts the voltage to 2.5 V, which is needed for the LCD. The decoder and microcontroller have a minimum operating voltage of 1.8 V. No level shifters are required between the receiver and decoder because the output signals of the receiver are open collector. Therefore, the voltage swing is determined by the baseband section.

The microcontroller is a type 8051. It also has an I2 C bus to allow easy communication with the decoder. Although the standard FLEX software is designed to operate on a 16-bit controller, the use of a less expensive eight-bit controller allows a reduction in the bill-of-material cost. The 8051 microcontroller used, a Philips model P87CL881H, has 32K of ROM and 512 bytes of RAM on chip. The use of I2C architecture permits a choice of the type of LCD display. This configuration allows standard LCD modules with the driver chip mounted on the glass to be used. In this case, the LCD driver includes a character generator plus display RAM.

The decoder receives input from the receiver or from a signal generator that stimulates the baseband signals. When a signal generator is used, the receiver part must be disconnected first. The baseband uses a Philips model PCD5008 FLEX decoder that connects to any receiver capable of providing a two-bit digital signal.

To aid in the power-management aspects of the design, the decoder operates the receiver in an efficient power-consumption mode. The receiver control sends a signal to the decoder that it may switch the receiver on using one or more warm-up states (up to a maximum of five), or it may shut it down using a maximum of two shutdown states.

The decoder synchronizes to a FLEX data stream; processes the received, demodulated information; performs the deinterleaving and error correction; selects calls addressed to the paging device; and communicates the message information to the host microcontroller. The decoder can handle up to 16 programmable addresses. Connection with the microcontroller is through a serial peripheral interface (SPI) bus. The host then can interpret the message information in an appropriate manner (numeric or alphanumeric). This function is performed by the FLEXstack software.

The EEPROM contains the pager attributes and is large enough to hold at least four addresses. The SRAM is added to provide enough storage for the FLEXstack software and message buffer. In an ideal solution, the capacity should be sufficient to accommodate four addresses and 16 messages of 200 characters per message.

The standard FLEXstack software from Motorola is ported to the 8051 controller. The reference system also requires a simple user interface providing basic pager functions.

The Development Environment

A good development system is essential for the success of the project. A major benefit of a good development board is the example setup of a high speed pager. The software must be able to be modified and the effects of the changes observed within the design using the emulator connection facilities (Keil) that are available. Ideally, it should be possible to use this development board with the existing emulators. A number of detailed development board features are particularly useful, including bit error rate (BER) measurement; visibility into software implementation and message transfer; communication and interfacing for ancillary circuits

(I2 C or SPI); measurement at interfaces between RF, host microcontroller and decoder; provision of basic user interface and testing/debugging facilities for developing the required user interface; and pager antenna design.

BER measurement is important when testing the sensitivity of the receiver. In the reference design, the microcontroller needs two data sources: one from the encoder and one directly from the baseband output of the RF generator. The development system includes software that automatically compensates for the delay through the receiver path and presents an automatic comparison of the received data. Thus, the performance of the receiver can be measured accurately.

Software implementation is at the center of all high speed pager designs. As the products become increasingly focused on software, the designer faces a growing task of writing and maintaining software functions that previously resided in hardware. It is already clear that decoding functions are increasingly moving toward pure software implementations. The trend is toward pagers that will operate under a number of different protocols and protocols that will have a common application programming interface (API). These capabilities then will allow the designer to develop a series of man-machine interfaces that operate with all of the protocols to realize a product range.

The use of I2 C architecture requires modifications to the standard FLEXstack software, but less on-chip RAM is needed in the controller for control of ancillary circuits. In addition, the size of the message storage may be chosen by changing the size of the EEPROM. The range of I2 C circuits also is large so a variety of options are available to allow the design to be optimized for cost, cosmetics and performance.

Another common demand of pager designers is the ability to perform measurements at the interfaces between the major system components. This capability allows the designer to see the signals that occur between the decoder, controller and receiver and understand how the information is transferred. For design debugging, the ability to compare existing signals with signals from a reference pager provides verification that the design is working within required limits.

The user interface is at the center of the pager software design concept. Even when the designer starts with the FLEXstack development kit from the Web, the notification procedures for the software still must be completed. These procedures permit the designer to invoke the proper functions of the user interface software.

The most important user interface functions in a pager relate to the storage and deletion of the messages. The API structure and control functions are especially important in this area, and it is essential to be able to monitor this area of the software closely. Other user-interface-controlled functions include configuring the decoder from the software for status messages, including low battery condition, synchronous mode and minute timer. Figure 3 shows how the software is used as the glue for the different elements of the pager design.

Pager antenna design can increase receiver sensitivity greatly. Tools are available to help in antenna design and network matching, which will help to optimize the overall design (taking into account proximity and human body effects).

The Future

Future developments in high speed paging will create roaming pagers. The hardware and software issues behind roaming are complex and require new approaches to pager design. A major element of these approaches will be the introduction of baseband controllers and decoders that are able to handle the extra load of more sophisticated roaming software.

Synthesized paging also will be an important design innovation in these new pagers. The end concept will be pagers that are not only flexible in terms of the paging protocol used by the operator, but that also are frequency independent within a particular range. The goal is to have pagers that will operate automatically not only on the different frequencies that are used in different areas, but will also include synthesis of the signal frequency. This capability then will allow the use of one crystal for all of the different frequencies. When this level is reached, paging devices then can be manufactured in continuous runs rather than the batches that are common currently. The emphasis then will have moved strongly from hardware to software as the basis for all designs. The importance of software will be increased further as single-chip concepts for the baseband are established and high integration concepts for the receiver appear.

Acknowledgment

Philips Semiconductors owns the copyright of this article, which was reprinted with permission.

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