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An Integrated GPS Receiver RF Front End
Philsar Electronics Inc.
Ottawa, Ontario, Canada
Global Positioning System (GPS) receivers are being used currently in many diverse applications, including low cost, battery-operated commercial applications that require inexpensive, high performance integrated components. The model PH1575 GPSRx application-specific IC (ASIC) is a dual-conversion L-band receiver RF front end developed specifically for portable GPS receiver applications. The bipolar silicon monolithic IC features good phase noise performance, low power consumption and one of the highest integration levels available. The unit utilizes an image-reject front end with dual downconversion and contains an integrated low noise amplifier (LNA), two frequency multipliers, a VCO, fixed-frequency dividers, automatic gain control (AGC) and a crystal oscillator. Image-reject mixers enable the use of low cost off-chip filters. The IC is packaged in a 48-pin TQFP package and is designed to operate from a 2.7 to 3.7 V DC supply.
The input is the L1 (1575.42) GPS signal. The output is a downconverted two-bit quantized signal ready for digital signal processing. The receiver features a total gain of over 120 dB with sign and magnitude digital outputs.
The ASIC's Configuration
The PH1575 GPSRx ASIC's block diagram is shown in Figure 1 . The input from a 50 W antenna is connected directly to the LNA input. This internal LNA nominally provides 18 dB of gain and a 2.5 dB noise figure to an external bandpass filter centered at 1575 MHz. If an external LNA is required near the antenna, the internal LNA is disabled by grounding pins 27 and 32, producing an approximate input current savings of 5.5 mA.
The output of the 1575 MHz bandpass filter is connected to the first RF strip via the RF_IN port. This strip features an image-reject mixer that provides 35 dB of low side image rejection. The on-chip VCO operates on the low side from 1475 to 1575 MHz. The first RF amplifier strip has a nominal conversion gain of 32 dB from 1575 MHz to the first IF and provides a differential output intended to drive a 600 W bandpass filter. A range of LO, first IF and second IF frequencies are possible, as shown in Figure 2 .
The output of the differential first IF filter drives the input to the first IF strip. The on-chip phase-locked loop (PLL) generates a first LO for downconversion to the second IF. Nominal conversion gain is 24 dB. The first IF has an output bandwidth of 15 MHz (nom) into a 1.2 kW differential load. Typically, a 2 MHz bandpass filter is used between the first and second IFs.
The second IF strip consists of a voltage-controlled AGC and a two-bit analog-to-digital (A/D) converter. The nominal 3 dB bandwidth is 40 MHz. The maximum gain of the AGC amplifier is typically 50 dB, and the AGC range is from +50 to –3 dB with a sensitivity of approximately 50 dB/V. Figure 3 shows typical gain vs. control voltage curves. The ASIC uses the magnitude bit of the internal A/D converter to control the AGC loop.
The normalized second IF output of the AGC amplifier is input to the A/D converter. The four-level A/D converter outputs magnitude and sign bits relative to three reference levels. SIGN_B output is a sign detector (for example, high for signals below the midpoint reference). The MAG bit is high for magnitudes greater than the A/D reference level (typically ±35 mV from the midpoint reference). The A/D sampling clock is driven by an external source and is independent of the first IF.
The A/D converter is used to sample the GPS clear and acquisition (C/A)-code signal, which has a spread spectrum signal bandwidth of approximately 2 MHz, hence the minimum A/D clock (Nyquist) rate is approximately 4 Msps. Typically, the GPS signal is oversampled.
To reduce digital interference, the digital outputs of the A/D converter are slew rate limited to a 20 ns rise time. This level limits the upper sampling rate of the converter to approximately 30 Msps. However, the converter sampling aperture has a 3 dB sampling bandwidth of greater than 100 MHz. As a result, the unit can be used to undersample the IF amplifier signal while oversampling the spread spectrum information.
The PH1575 ASIC features an integrated VCO with an on-chip resonator. The VCO output drives the first-stage image-reject mixer LO and the prescaler chain. The prescaler produces two divided-down LOs. The first fLO1 signal is at N = 30. The second signal is the PLL phase detector variable input fREF, which is generated at N = 30, M = 5.
The ASIC has a self-contained crystal oscillator with a range of frequencies from 9.8 to 10.3 MHz, depending on the externally supplied crystal. As an option, the device may use an external reference input. The internal or external reference frequency is compared with the prescaler chain output via an on-chip phase-frequency detector. This detector tracks over ±2p radians. The positive edge-triggered phase detector drives a charge pump that produces 100 mA/2p radians. This charge pump drives an off-chip passive loop filter that sets the loop bandwidth of the PLL. The loop filter's output drives the VCO tune port directly. The VCO sensitivity is approximately 100 MHz/V.
The PH1575 ASIC features three modes of operation: an all-on default mode; Rx off, PLL and external clocks on; and all off except the ASIC power control interface. The IC is reset automatically on power up. Typical input currents for the three modes are 49, 4 and 23 mA for the normal (LNA active), standby and clock modes, respectively.
The TQFP-48 package has 12 leads per side and measures 7 x 7 mm square and 1.4 mm thick (max). The lead pitch is 0.5 mm. The package is designed for surface-mount applications.
The PH1575 GPSRx ASIC's 3 V operation and power-down capability are designed specifically for low cost, battery-operated GPS receiver applications. The high level of integration results in fewer of the receiver components being mounted off chip, saving substantial PCB space and reducing the cost of these components. In addition, the selection of the first IF allows both image and LO leakage filtering to be accomplished with a low cost miniature dielectric RF filter, while the IF is low enough for low cost LC IF filtering. Also, the use of a double-balanced mixer provides enhanced LO rejection, permitting simple low cost front-end filters to be used to reduce LO reradiation.
The inclusion of the internal LNA and VCO both lowers cost and reduces overall system power consumption. The optional use of the internal LNA, in the case where an LNA is required at the antenna, produces additional power savings. Having the VCO on chip eliminates the cost of external varactors and the noise that is associated with these components. Also, the internal crystal oscillator further reduces the need for external components.
Finally, the use of a two-bit A/D converter improves the overall receiver noise figure by approximately 1 dB over a more traditional one-bit A/D configuration. The 50 dB gain control provided by the AGC compensates for gain variations from low tolerance components automatically. This additional flexibility is critical in reducing manufacturing costs. The AGC also can compensate for the variation in external LNA models that can be selected for various applications.
For designers attempting to create the lowest cost, lowest power and most integrated solution for a GPS receiver, the PH1575 GPSRx ASIC is an ideal choice. The device currently is available in high volume production quantities for less than $10. Consult the factory for delivery status.
Philsar Electronics Inc.,
Ottawa, Ontario, Canada
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