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Noise XT introduces SLC ultra-low jitter/dual clock synthesizer

Test & Measurement

Noise eXtended Technologies (Noise XT) has introduced the 2 MHz to 7 GHz SLC ultra-low jitter/dual clock synthesizer. The SLC is an affordable single or dual clock USB synthesizer with outstanding jitter in a small package. With a noise floor of -170 dBc/Hz at 10 MHz, the SLC has the lowest phase noise of any synthesizer in a compact, low cost package. The SLC measures just 85 x 110 x 200 mm.

“The SLC is designed to provide excellent clock or LO (local oscillator) substitution signals to semiconductors where jitter and noise really matter. Typically, the SLC will be used to drive data converters (ADC and DAC), direct digital synthesizers (DDS) or high-speed FPGAs and serial links to achieve the highest performance,” said Guillaume de Giovanni, President, Noise XT.

Most of the clock sources on the market today are either noisy digital boards or traditional signal generators—losing quality at useful frequencies. To discern the quality of a clock source, a typical figure is the amount of jitter, which is related to phase noise.
The SLC offers two clean clocks in a single compact package to achieve low jitter measurements down to -170 dBc/Hz at 10 MHz and 40 fs (femtoseconds) RMS on a 155 MHz clock for example.
Need for low jitter driving market to better solution
The SLC serves R&D and production engineers working in the semiconductor industry where accurate timing matters. Wireless applications, particle colliders, digital semiconductor testing, and network time synchronization are a few of the many applications. Products that will benefit most from using the SLC are digital transceivers used in Software Defined Radio (SDR) applications and high-speed semiconductor testers. The SLC is used as either a local oscillator or as a clock in single or dual configurations allowing smaller footprint per channel.
            In jitter measurements, the lower the jitter, the more accurate the time will be, enabling more bandwidth, and better signal-to-noise (SNR) ratio. The result is fewer transmission errors and better detection of weak signals.
New applied technology allows better clock performance
 The SLC uses the latest component technology to maximize the cost/performance ratio on a 100 x 160 mm internal board. The unique combination of multi-DDS (Digital Direct Synthesis) with PLL (Phase-Locked Loop) is used to achieve the SLC’s ultra-low jitter performance.
            “To our knowledge, no one else offers the multi-DDS plus PLL combination to achieve this level of jitter performance at such a low cost,” said Laurent Adrien, SLC lead designer.
Key Specifications of the SLC

  • -170 dBc/Hz phase noise floor (equal to using pure crystal oscillators)
  • Up to 135 dB SNR for ADC/DAC testing
  • 2 MHz to 7 GHz wideband coverage
  • USB / SPI / Ethernet controlled
  • Single or dual configuration in the same compact housing
  • Best performance / price ratio of the market

Price and availability
The SLC Low-noise Compact Dual Synthesizer will be available in 8 weeks upon receipt of order with first shipments in Q4. Pricing starts at 3 950 € and can be ordered directly on our website store at To contact Noise XT, visit


Source: Noise XT

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