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Ball Grid Arrays: A DC to 31.5 GHz Low Cost Packaging Solution for Microwave and mm-wave MMICs

A ball grid array surface-mount packaging technology for applications including packaging of GaAs MMICs

Ball Grid Arrays: A DC to 31.5 GHz Low Cost Packaging Solution for Microwave and mm-wave MMICs

The VIA/PAK™ ball grid array (VBGA) surface-mount packaging technology for high frequency RF and mm-wave applications is described in this article. The package was developed for the frequency range from DC to 31.5 GHz for applications including packaging of GaAs MMICs for satellite-based terminals such as very small aperture terminals, point-to-point radios, local multipoint distribution systems, phased-array communication satellites, and radar and ground terminals. The VBGA package is a thin-film ceramic chip carrier with a VIA/PLANE™ base material, which comprises a single-layer ceramic interconnect substrate with solid tungsten-copper vias. The package is suitable for both wire bond and flip-chip MMICs. This article discusses the electromagnetic modeling, design, manufacture and electrical performance of the VBGA package.

M.P.R. Panicker, D. Douriet, M.S. Hyslop and N.L. Greenman
Micro Substrates Corp. (MSC)
Tempe, AZ

The burgeoning wireless market encompassing voice, video and high speed data transfer is creating an ever-increasing demand for high speed GaAs semiconductor ICs. In turn, this requirement has created a need for low cost, easy-to-use MMIC packages in a single-chip format for use with known good die and multichip formats for modules such as transceiver terminals. Conventional multilayer ceramic and metal boxes have not kept pace with the falling prices of GaAs semiconductors. In addition, these technologies do not offer a surface-mount solution conducive to miniaturization and automated pick-and-place assembly and test. Conventional surface-mount packages for microwave devices include J leads, ribbon bonds and cutouts in the PCB to reduce the effective lead length and its associated inductance. In all of these cases, the assembly is cumbersome and expensive. The leads use up to an additional 30 to 50 percent of the PCB space beyond the package footprint, depending on the carrier size. The packages also are inherently expensive.

The VBGA is a low cost, leadless ceramic package in a true surface-mount configuration using noncollapsing, hard balls made of copper-silver eutectic alloy. Alternatively, materials such as high temperature alloys or metals such as copper can be used for the balls. VBGA packages are manufactured using semiconductor fabrication techniques to achieve the cost advantages of array processing. The base for these packages is a single-layer, ceramic interconnect substrate with tungsten-copper vias.

VBGA Advantages
The VBGA package provides many advantages over conventional MMIC packaging, including lower cost as a result of array processing and a true through-via, surface-mount configuration. The package is simple to assemble, providing self-aligning reflow and allowing assembly at the wafer level. The VBGA package features the smallest MMIC package footprint because there are no ribbon bonds. The absence of ribbon bonds makes multiple MMIC module assembly inexpensive. In addition, the package is well suited for flip-chip assembly and provides good heat dissipation through tungsten-copper vias.

The Package Design
The VBGA package is designed using a ceramic interconnect substrate with solid tungsten-copper vias.
1,2 The ceramic is 99.6 percent alumina. Alternatively, aluminum nitride (K = 170 W/mK) can be used when thermal management becomes a major consideration. While most semiconductor devices require custom package designs, a generic package was designed for this work as a test vehicle to be evaluated by design engineers. Tables 1 and 2 list the VBGA package design goals and mechanical specifications, respectively. Figure 1 shows the test package layout.

Table I
Design Parameters

Frequency of Operation (GHz)

DC to 30

Number of RF Ports

three; two opposing and one adjacent

Number of Bias Ports

five; three on side without RF port and two around the adjacent RF port

Insertion loss (RF port) (dB)

< 0.5

Return Loss (dB)

< 15

Port-to-port RF Isolation (dB)

> 40

Ball Height (mm)


Ball Shape


Lid Type

ceramic with epoxy preform


moisture resistant

Overall Size (mm2 )


Overall Height (mm)

0.76 without the lid

Die Attach Area (mm)



wire-bondable gold


Table II
Mechanical Specification

Package Size


0.250 x 0.250


6.35 x 6.35

Die Size


up to 0.078 x 0.078


up to 1.98 x 1.98

Number of 28 GHz Ports


Number of RF/DC Ports


Carrier Height


0.030 nominal, including the ball array


0.75 nominal, including the ball array

Die attach

epoxy, solder or eutectics including Au-Sn and Au-Ge


ceramics or plastics with epoxy preform

The design was completed using electromagnetic modeling techniques with Sonnet em 3D™ software. The package design relies on the optimization of transitions between coplanar structures because these structures present a convenient method of transferring signal and ground currents between the different transmission media (mainly the bottom and top package surfaces, transitional air and dielectric substrate). The problem was addressed by breaking down the structure into transitions, as shown in Figure 2 , which include the Duroid to the bottom surface of the ceramic through a package interconnect and the bottom surface of the ceramic to the top surface of the ceramic through a via and slot structure. The unique substrate technology allows the inclusion of solid-filled tungsten-copper vias and slots to create impedance-controlled structures in a ceramic substrate. A coplanar field structure was maintained along the entire RF port geometry.

The design effort focused on the optimization of return loss through an RF transition. The actual modeled RF port geometry includes a portion of the Duroid coplanar structure, the ball, the coplanar structure on the bottom surface of the package, the via and two slots, and the coplanar structure on top of the ceramic surface up to the point where a ribbon bond interfaces with the device mounted in the package. The electromagnetic (EM) model was verified against internal factors such as wire bonds using emgen™ circuit analysis software. The output generated by the EM simulation software for the RF port was simulated as a two-port device. The device's configuration is shown in Figure 3 .

The accuracy of the model was limited because the model complexity results in impractical solution times. For example, as the model grew, when attempting to include more elements or when the resolution was increased to define smaller features, the memory and computational requirements grew exponentially to the point where the modeling was not possible due to memory limitations or impractical solution times.

Another factor that affected the accuracy was the planar three-dimensional layout constraints. The actual shape of the balls, vias and metallization pattern could only be approximated. The mapping of the balls and braze fillets into an equivalent geometry is particularly critical.

Figure 4 shows the geometry of the RF feedthrough portion of the package. The RF feedthrough is a 0.12 mm diameter tungsten-copper via placed between two tungsten-copper slots. The thickness of the substrate is 0.37 mm. The EM model predicts a maximum return loss of 15 dB over the design range of DC to 30 GHz. The insertion loss is close to 0 dB over this range. Accordingly, the RF port design was frozen and used for the described test vehicle.



Figure 5 shows the EM-simulated S parameters for the package. The slot-and-via pattern was designed so that the insertion loss is less than 0.3 dB per port and return loss is less than 18 dB over the DC to 30 GHz range.

Package Construction
The package was produced on a VIA/PLANE substrate using thin-film processing techniques. Holes measuring 0.1 mm in diameter and slots measuring 1.12 x 0.15 mm wide were drilled in sintered 99.6 percent alumina substrates using a CO
2 laser. This technique eliminates any shrinkage during further processing and, thus, ensures the precise registration of vias necessary to meet the alignment requirements of subsequent thin-film processing steps. The vias then were filled with tungsten and sintered in an H2 /N2 reducing atmosphere. This step resulted in a via fill with approximately 20 percent porosity. In a second step, the pores were filled by infiltrating molten copper at approximately 1100°C in a reducing atmosphere. The resultant tungsten-copper composite vias are pore free and form the electrical connections with thermal expansion characteristics matched to those of alumina. The via-filled substrate was lapped and polished to achieve the required flatness, surface finish and design thickness of 0.37 mm.

VIA/PLANE manufacturing panels measuring 50 mm square were used to produce the test vehicles that yield 49 packages. Thin-film titanium, molybdenum and nickel were deposited on both sides of the substrate using an E-beam process, which involves the evaporation of the material to be deposited. The significant advantage of this approach is the high deposition rate.

The thin-film metallurgy used was deposited. Approximately 2500 Å of titanium was deposited as the adhesion layer, followed by approximately 2500 Å of molybdenum as a diffusion barrier. Three to 3.5 mm of nickel was deposited as the brazing layer. This metallization sequence was provided on both sides of the substrate and photopatterned using conventional photolithography. The bottom side was photopatterned with a second mask to etch away only the nickel and molybdenum around the bump sites to form a braze dam, which will contain the material used to braze the balls. The result is a donut pad of titanium around each ball location.

Ball Attachment
The ball material selected was copper-silver eutectic alloy, which will not collapse during assembly to the PCB. Using computerized numerically controlled milling, a graphite fixture is machined with a pocket to accept the 50.8 mm square substrate and an array of shallow holes for each of the balls to be attached. The depth of the holes allows the substrate to touch the ball preforms when placed into the fixture pocket. Cu/Ag ball preforms measuring 0.46 mm in diameter are vibration loaded into the fixture and excess balls are removed. The substrate then is placed into the pocket and aligned by two notches in the fixture. A graphite lid is placed on top of the substrate. Weight is applied to the substrate to ensure that, when the
Cu/Ag ball preforms melt, the substrate will drop to the bottom of the pocket. The graphite fixture is loaded onto a belt furnace and brazed under a reduced atmosphere of H2 /N2 at a carefully controlled temperature profile. The Cu/Ag preforms melt, forming a hemispherical bump with a final height of 0.38 mm ±0.025 mm and a base diameter of 0.51 mm. The base diameter is controlled using a braze dam around each of the desired bump locations on the substrate. This dam is created by exposing the titanium metal layer around the desired bump pad in a donut-shaped geometry. This method produces bump heights with tight height distribution and good coplanarity. The hard bumps can withstand process temperatures of up to 750°C. Figure 6 shows the VBGA package's cross section.

The 50 mm array of packages is plated with a minimum of 1.3 mm of gold on the die-attach side and 0.13
to 0.25 m m of gold on the bump side per MIL-G-45204. Figure 7 shows the individual VBGA packages. Figure 8 shows the packages manufactured in an array format.


VBGA Testing
To determine the actual performance of the package's high frequency ports, the top metallization pattern was modified to provide a 50
W grounded coplanar waveguide (CPW) connecting the two RF ports opposite each other. An alternative method would be to mount a 50 W chip on a package with the regular metallization pattern and provide connections to the RF ports through wire or ribbon bonds. However, this method would have rendered the measurements greatly dependent upon the bonding technique used and, consequently, make it difficult to reproduce.

By avoiding device-to-package interconnection issues, no assumptions were made regarding the type of connection that could be used eventually, including wire bonds, ribbon bonds or flip-chip. The flexibility of VBGA thin-film technology allows the incorporation of any chosen transition to the MMIC RF ports. At the system level, the designer has the freedom to use the most efficient interconnection technique.

The package performance was evaluated by coplanar probe measurements. The test equipment used was a vector network analyzer with 0.010" (0.254 mm) pitch coplanar probe tips. The test cables and probes were calibrated with a short-open-load-thru method using the CS-5 reference substrate.

A ceramic substrate, shown in Figure 9 , was designed to mount the VBGA package, including co-planar transitions from the 0.010" (0.254 mm) pitch of the probes to the 0.038" (0.965 mm) pitch of the package's RF port balls. The package was soldered to the test substrate using regular Sn63 solder paste. By calibrating to the probe tips and minimizing the transitions to the package, an accurate evaluation of the VBGA package performance, attachment and transitions was achieved.


Test Results
Figure 10 shows the S parameters as measured by the described setup. The test setup was calibrated prior to measuring the VBGA to ensure its stability. The data provided are for two ports and include the coplanar transitions into the package for each RF port. The insertion loss is less than 0.3 dB per port from DC to 30 GHz and 0.5 dB per port at 31 GHz. The return loss is better than 15 dB in the DC to 37 GHz range and, generally, is better than 17 dB.

The package shows less than 1 dB per port of insertion loss and better than 15 dB of return loss in the 33 to 35 GHz range. The package's S21 and S12 characteristics were identical as were the S11 and S22 characteristics over the measured ranges.

The VBGA described in this article is a true surface-mountable, thin-film, low cost ceramic packaging solution for microwave and mm-wave MMICs. The package demonstrates good insertion and return loss characteristics in the DC to 31.5 GHz range. It is suitable for all conventional volume assembly processes, such as tape-and-reel, pick-and-place, in addition to wafer-level assembly processes. The test data compare well with the electromagnetic model.

The authors wish to thank James Schirmer, Yaozham Lieu and John Leitner of Hughes Aircraft Co., Los Angeles, CA, for their useful suggestions and assistance during the measurements. The Sonnet em 3D simulation software and emgen circuit analysis software are products of Sonnet Software Inc., Liverpool, NY. The vector network analyzer is the model HP8722D from Hewlett-Packard Co., Santa Rosa, CA. The model 40A-GSG-250-DP coplanar probe tips and the CS-5 reference substrate are from GGB Industries Inc., Naples, FL.

1. M.P.R. Panicker et al., US Patent No. 4,492,076.

2. C.J. Mattie, "Advanced Alumina: A Manufacturing Medium for Microwave Oscillators and Amplifiers," Microwave Journal, Vol. 36, No. 2, February 1993, pp. 64–74.

3. D.M. Mattox, "Film Deposition Using Accelerated Ions," Electrochemical Technology, No. 2, 1964, pp. 295.

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