FETs that Address the Linearity Challenge
Laterally diffused metal-oxide semiconductor FETs designed for use in base station applications are featured on this month's cover
FETs that Address the Linearity Challenge
RF Power Products
Morgan Hill, CA
The volume of cellular base station traffic in today’s market is skyrocketing. This increasing traffic can be handled only by improving the linearity of the RF power amplifiers, which are the nucleus of these base stations. Historically, these power amplifiers operated class AB, offering an acceptable balance between linearity and efficiency. However, in order to achieve the desired increase in linearity, a bipolar transistor-biased class AB mandates that these amplifiers operate over specific output power levels, whereas a lateral FET offers more flexibility. This article describes the device structure and electrical characteristics of laterally diffused metal-oxide semiconductor (LDMOS) FETs, and discusses how these particular FETs address the linearity challenge.
A cross-sectional view of an LDMOS FET is shown in Figure 1 . The FET is a three-terminal device, consisting of a p-type semiconductor substrate in which two n-type regions (source and drain) are formed. The gate region is separated from the conducting channel by a thin layer of SiO2 , which is grown onto the channel. When a sufficiently large positive voltage is applied to the gate with respect to the source, an inversion layer (or channel) is formed between the two n-type regions. The source and drain then are connected by a conducting surface n-channel through which current can flow. The LDMOS FET operates in the enhancement mode. In other words, with a positive-polarity drain voltage applied, no drain current flows until a positive gate voltage enhances a channel across the p well. In operation, the channel current is modulated by the AC signal impressed upon the gate.
The source is brought to the bottom side of the die in order to lower source inductance and improve the intrinsic gain. In addition, the die can be attached to the flange of a transistor package directly, thereby reducing thermal resistance. Gold metallization and silicon nitride passivation are incorporated to ensure good device lifetime and reliability.
Channel current in an enhancement-mode MOSFET is controlled by a voltage applied to the gate electrode. By virtue of the isolated gate electrode and no forward-biased p-n junctions, as is present with all bipolar transistors, the gate draws no current. The resulting high input impedance allows a resistive divider network to provide proper DC bias. This configuration reduces complexity and cost compared to an active low impedance network required to bias the emitter base junction of a bipolar junction transistor (BJT).
Another advantage of the MOSFET as compared to the BJT is its thermal stability. Drain current in the saturation region of the current-voltage
characteristics is given by
ID = k(VGS – VT )2
k = scale factor, kµ T–3/2
VT = threshold voltage
The scale factor depends on the geometry of the FET, gate oxide capacitance and carrier mobility. Since the scale factor has a negative temperature coefficient, the drain current decreases with increasing temperature. The threshold voltage also is temperature dependent. However, under large drain currents, the combined effect produces a drain current that is inversely proportional to temperature, resulting in a complete absence of thermal runaway. The drain current vs. gate voltage of the model PTF-10004 LDMOS device over temperature is shown in Figure 2 .
The LDMOS FET process has improved RF performance significantly by lowering the drain-to-gate capacitance (Crss ). This characteristic not only improves gain, but also results in better device stability. In addition, having the source on the bottom of the die eliminates source inductance due to bond wires, which are required on vertical MOSFET structures. Source inductance acts as degenerative feedback, which lowers RF gain. Comparing a BJT with similar power capability, LDMOS transistors offer 3 dB gain improvement.
A plot of gain vs. input power for the model PTF-10004 device biased class AB is shown in Figure 3 . The bias current is optimized to achieve a maximally flat gain response. The gain stays constant from a low input power to the input level at which the device begins to compress. These characteristics can be an advantage in multichannel systems where high peak-to-average power ratios and low phase distortion are required.
Two-tone, third-order intermodulation distortion was compared between the FET and BJT. The BJT has an optimum intermodulation performance near its rated power (45 W peak envelope power (PEP)) that worsens as the output power is varied above and below this level. The FET exhibits poorer intermodulation at the upper end of its power rating but surpasses the BJT below 30 W PEP. The LDMOS transistor intermodulation distortion has a monotonic slope with output power. The comparison results are shown in Figure 4 .
Figure 5 shows the spectrum of an eight-tone measurement taken on thePTF-10004 device at 50, 25 and 5 W PEP output, respectively. The graphs show that as the output power is decreased, the intermodulation distortion products improve.
This article has demonstrated that the LDMOS transistor offers improved gain performance, better thermal stability and improved intermodulation distortion when output power is backed off as compared to the BJT. When biased at an optimum quiescent current, the FET’s gain can be held constant over a wide range of input power, allowing the use of a class AB stage where a class A stage was required previously.
Currently, there are nine devices in the LDMOS family of products operating from HF to 1000 MHz that exhibit power outputs ranging from 6 to 85 W. All of these LDMOS products incorporate gold metallization and gold bond wires, resulting in extremely high mean time between failures and greater reliability.
The LDMOS products are especially well suited for today’s high linearity demands of base station applications in the 800 to 1000 MHz band, providing two-tone intermodulation distortion products of –30 dBc or better. Gain and efficiencies range from 11 to 16 dB and 50 to 55 percent, respectively. These LDMOS products are offered in surface-mount, flange and pill packages and are provided in unmatched or matched, single-ended or push-pull configurations. Currently, LDMOS transistors are being developed with power handling capabilities up to 85 W for operation in both the 900 MHz and 2 GHz ranges.
The company would like to thank Scott Porro, applications engineer, RF Power Products, Morgan Hill, CA, and Jan Johansson, process engineer, Wafer Fabrication, Kista, Sweden, for their contributions in preparing this article.
1. S.M. Sze, Physics of Semiconductor Devices, John Wiley & Sons, 1981.
2. P. Horowitz and W. Hill, The Art of Electronics, Second Edition, Cambridge University, 1980, 1989.
Ericson Components, RF Power Products,
Morgan Hill, CA