- Buyers Guide
Focus on Signal Integrity and High Speed Digital Design in Technical Conference and Workshops at EDI CON 2014
Signal integrity engineers and high speed digital engineers of multi-gigabit links are experiencing design challenges often associated with microwave frequencies. As a result, test instrument and simulation software vendors are providing solutions to tackle high speed channel characterization and design. The EDI CON technical tracks have been expanded in 2014 to include a new dedicated signal integrity, high-speed digital and EMC/EMI modeling/measurement track featuring papers on the challenges facing high-speed digital designers at the chip, package and board levels. The added HSD/EMC measurement and modeling track will take place on Thursday morning, April 10th This track comprised of eight, 20 minute peer-reviewed presentations will complement related papers in the design tracks and various afternoon workshops held throughout the entire conference.
Specific papers on SI, HSD and EMC/EMI include:
Impact of RF solid state switch in phase noise and jitter test measurement on the ATE
It is very common to find relays on the ATE test and application board. The relay is mainly used as a switch to connect the DUT to different test circuits for measuring different test parameters. Since the relay is part of the test circuit, the performance of relays also affects the measurement result. The relay selection becomes even more critical if we wanted to measure high speed signals. This paper discusses the impact of the solid state switch (SSR) relays used in testing a DUT output phase noise and RMS jitter result. The measurement is performed using the Agilent E5052B source analyzer and the DUT is a precison clock jitter cleaner IC with an output frequency from 100MHz up to 3GHz. Insertion loss and isolation are two important parameters to inspect in this case study. The paper also compares the result obtained using the RF electromechanical relay (EMR) and solid state switch (SSR) and examines the pros and cons of these two type of relays in testing the phase noise and jitter test, with emphasize of ATE board design and applications. Presented by Yean Feng Chek (Texas Instrument)
Simulation and Measurement of Power Supply Common-mode Rejection
Modern switched mode power supplies have faster switching time which leads to higher electromagnetic energy at higher frequencies. In this paper, we analyze via simulation and measurements the common-mode rejection ratio as well as the far field radiation of a power supply. Results from different simulation tools are compared with measurement data at 10MHz to 2 GHz. A design guideline on selecting common-mode rejection components in power supply is also presented. Presented by Hongmei Fan, (Cisco Systems - China)
Practical Guide to Making Advanced Jitter Measurements
To characterize high-speed digital links, jitter measurements are key to ascertain the quality of the signal being transmitted and yield a quick view of the bit error ratio (BER) that can be supported by the link. The measurement of jitter, even if the user is provided a one-button interface, is a sophisticated affair taking into account clock recovery and knowledge of phase locked loops (PLLs), jitter decomposition techniques and assumptions for them, crosstalk and its effects, and waveform statistics that require different approaches. This presentation will review the analysis of a digital link and jitter decomposition, introduce whole eye-diagram analysis, and guide engineers through details and considerations required for valid jitter measurements. After viewing this presentation, engineer will better understand the measurement of jitter as an engineering process. Presented by Min Jie Chong, (Agilent Technologies)
FFT-based time-domain EMI measurements: benefits, challenges and CISPR emission standard references
Conventional EMI measurement systems can only measure disturbance signals within the resolution bandwidth within a stated measurement time, whereas FFT-based time-domain EMI measurement systems allow a much wider part of the observed spectrum to be analyzed simultaneously. However if the CISPR emission standard does not refer to the basic standard latest edition 3 of 2010 and Amendment 1, these measurements can be used for preview or pre-compliance testing only. The referencing of new releases of CISPR emission standards is important. The basic standard comes into force with dated or undated normative references in the product family standards. Presented by Volker Janssen, (Rohde & Schwarz)
High speed DDR memory debug and characterization with a Mixed Signal Oscilloscope
Separating read and write cycles for DDR data characterization is key to enabling electrical and timing measurement as per the JEDEC specification. A mixed signal oscilloscope (MSO) addresses this measurement challenge with robust read and write separation and powerful trigger condition to accurately characterize data margin. This presentation describes the tools and features of an MSO that can be optimized to configure a full debug system. The presentation will also reveal MSO probing options and new DDR debug tool that will allow a designer to go beyond basic DDR compliance testing. Presented by Min Jie Chong, (Agilent Technologies)
Synchronization of multiple oscilloscope measurement systems to sub-ps levels.
The proliferation of high data demand across long haul communication media has led to the need of new coherent modulation techniques to achieve terabits of data per second. Trends such as spatial modulation have begun to move from science experiments to mainstream technologies. While the techniques push the edge of the technology, measuring data rates at terabits per second causes new measurement science to be enabled. No longer is it enough to look at one differential lane at high data rates, it has become a requirement to view ten to forty lanes at once with extremely tight channel to channel correlation. This paper will discuss techniques to achived channel to channel jitter of sub-300 fs on up to forty channels. Presented by Brig Asay, Agilent
Automate Multilane Gigabit Serial Testing
Many high-speed digital interfaces are adopting multilane high-speed signals to achieve the required data throughput. They include the PCI Express interface which supports up to 16 lanes operating at 8 GT/s used in graphics processing applications, the HDMI 2.0 interface with 3x lanes at 6 Gb/s for high resolution displays and the MIPI M-PHY interface that scales up to 4 lanes at 5.8304 Gb/s for mobile applications. Validating a multilane interface increases the effort and complexity using an oscilloscope as engineers must manually connect the signals under test into the limited input channels of an oscilloscope. In addition, there are various test conditions - design operating modes, voltage, temperature, etc. that they must test, requiring user intervention to get testing started. Presented by Min Jie Chong, (Agilent Technologies)
Uncertainty and stability in true differential-drive measurements
The high speed characterization and model development for many high-speed components may include differential return loss, transmission and mode conversion measurements under real-world drive conditions, particularly for digital drivers, buffers, and related components. As such, true differential drive at large signal levels is often needed and measurements have sometimes been a challenge. To minimize re-calibrations and to have confidence in the data, a highly stable method of making these measurements and an understanding of any uncertainty degradation can help. The mechanisms of importance will be discussed along with an implementation of true-differential drive S-parameter measurements with phase drive accuracies of better than a few degrees, at frequencies for 50 Gb/s systems and beyond, more than 24 hours after calibration and with relatively minor uncertainty degradation relative to single-ended measurements. This behavior can allow more accurate characterization and model generation including the presence of fewer causality problems. Presented by Jon Martens, (Anritsu)
Optimizing Chip-Module-Board Transitions Using Integrated EM and Circuit Design Simulation Software
3D electromagnetic simulators are commonly used to help design board-to-chip transitions. AWR has made this process easier with the introduction of Analyst™, a 3D FEM simulator integrated within its circuit design environment. This presentation highlights how the new features in Analyst can be used to optimize a chip-module-board transition. The transition discussed is typical of a high-speed analog signal line, going from a high performance system board, onto a BGA mounted module, through the module, and onto an RFIC chip by means of bond wires. Presented by John Dunn, (AWR)
SI Measurements and channel characterization - Agilent Workshop
Date: Tuesday, April 8, 2014
Time: 1:30 PM - 2:15 PM
Part 1: Advanced Techniques for Characterizing a 28 Gb/s SERDES Channel
A design methodology will be demonstrated for 28 Gb/s SERDES channels using the Xilinx Virtex-7 Transmitter (Tx) to show the required trade-offs that enable robust performance that is easy to verify with measurement. 1-port fixture measurements taken on both a frequency domain VNA and a fast step edge time domain TDR reflectometer will be compared with previous full path probing and 2x fixture measurement methods to enable reliable fixture removal. Tx and Rx characterization provide information on the spectral demands for the channel; simulation of cables, connectors, vias, PCB transmission-lines, and package ball-out determine critical elements for performance; physical routing along with test structures and interposers will determine the ability of measurements to verify performance. Combining design and measurement methodology enables the capture of 28 Gb/s Tx waveforms at the BGA package bumps even with a lossy fixture path connection to the measuring oscilloscope.
Part 2: Signal Integrity Measurements Technologies in 10G-32G Digital System
R&D teams not only in industry products such as optical communication, data communication and computers, but also aerospace and defense are looking to meet the challenge of designing and measurement 10G-32G digital system. When testing these high speed digital system, the presenter discusses the tools and techniques behind testing the signal integrity of high speed backplane, high speed SerDes and interface bus, as well as how to test power distribution networks and clock circuits.
Many different instruments and measurements method are required to characterize high speed data links and this paper describes these technologies, instruments and methods. Presented by Deng Liang Sun, Agilent Technology